DivMMC Trap Enable 2 Register: Difference between revisions

Revision as of 11:20, 4 February 2020

Number	TBRegisterNumber::$B4
Readable	TBRegisterReadable::Yes
Writable	TBRegisterWritable::Yes
Short Description	ShortDesc::DivMMC trap configuration

(hard reset = 0x1B)

   bits 7:5 = Reserved, must be 0
   bit 4 = (trap, instant) enable 0x3D00 - 0x3DFF
   bit 3 = (trap, delayed) disable 0x1FF8 - 0x1FFF
   bit 2 = (trap, instant) enable 0x04CB, 0x056B
   bit 1 = (trap, delayed) enable 0x04C6, 0x0562
   bit 0 = (trap, delayed) enable 0x0066

(new register since core3.1.0)