DivMMC Trap Enable 1 Register: Difference between revisions

Revision as of 11:17, 4 February 2020

Number	TBRegisterNumber::$B2
Readable	TBRegisterReadable::Yes
Writable	TBRegisterWritable::Yes
Short Description	ShortDesc::DivMMC trap configuration

(hard reset = 0x83)

   bit 7 = (trap, delayed) enable 0x0038
   bit 6 = (trap, delayed) enable 0x0030
   bit 5 = (trap, delayed) enable 0x0028
   bit 4 = (trap, delayed) enable 0x0020
   bit 3 = (trap, delayed) enable 0x0018
   bit 2 = (trap, delayed) enable 0x0010
   bit 1 = (trap, delayed) enable 0x0008
   bit 0 = (trap, delayed) enable 0x0000

(new register since core3.1.0)