Difference between revisions of "CPU Speed Register"

Revision as of 23:20, 4 December 2019

Number	$07
Readable	Yes
Writable	Yes
Short Description	Sets accelerated clock speed, reads actual speed.

Read:

Bit	Function
7-6	Reserved
5-4	Current actual CPU speed
3-2	Reserved
1-0	Programmed CPU speed

Write:

Bit	Function
7-2	Reserved, must be 0
1-0	Set CPU speed (soft reset = %00) %00 = 3.5MHz %01 = 7MHz %10 = 14MHz %11 = 28MHz (works since core 3.0)

The CPU throttling from 14MHz to 7MHz is not happening in core 3.0+ any more (but if any configuration would require it, or 28MHz mode will be implemented with throttling, it can be seen by reading bits 5-4). The 3.5MHz speed limit when Expansion Bus is enabled is of course visible in bits 5-4 too.

The 28MHz with core 3.0.5 is adding extra wait state to every instruction opcode fetch (i.e. instruction like NOP will take 5T instead of regular 4T), there is some chance this may be improved in the future.

@@ Line 27: / Line 27: @@
   %01 = 7MHz
   %10 = 14MHz
-  %11 = 28MHz (reserved for future, currently gets dropped to %10 14MHz)
+  %11 = 28MHz (works since core 3.0)
 |}
-The CPU throttling from 14MHz to 7MHz is not happening in core 3.0+ any more (but if any configuration would require it, or 28MHz mode will be implemented with throttling, it can be seen by reading bits 5-4).
+The CPU throttling from 14MHz to 7MHz is not happening in core 3.0+ any more (but if any configuration would require it, or 28MHz mode will be implemented with throttling, it can be seen by reading bits 5-4). The 3.5MHz speed limit when Expansion Bus is enabled is of course visible in bits 5-4 too.
+The 28MHz with core 3.0.5 is adding extra wait state to every instruction opcode fetch (i.e. instruction like NOP will take 5T instead of regular 4T), there is some chance this may be improved in the future.