Pi I2S Clock Divide Register: Difference between revisions
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core 3.0 changes/refresh |
fixing default value Hz result... (my math, argh) |
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| Line 8: | Line 8: | ||
clock divider = 538461 / SampleRateHz - 1 | clock divider = 538461 / SampleRateHz - 1 | ||
i.e. SampleRateHz = 538461 / (clock divider + 1) | |||
The default value corresponds to | The default value corresponds to ~44871Hz sample rate. | ||
Revision as of 16:30, 12 November 2019
| Number | TBRegisterNumber::$A3 |
|---|---|
| Readable | TBRegisterReadable::Yes |
| Writable | TBRegisterWritable::Yes |
| Short Description | ShortDesc::Pi I2S clock divide in master mode. |
bits 7:0 = Clock divide sets sample rate when in master mode (soft reset = decimal 11)
clock divider = 538461 / SampleRateHz - 1 i.e. SampleRateHz = 538461 / (clock divider + 1)
The default value corresponds to ~44871Hz sample rate.