Pi I2S Clock Divide Register: Difference between revisions
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core 3.0 changes/refresh |
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Revision as of 11:39, 12 November 2019
| Number | TBRegisterNumber::$A3 |
|---|---|
| Readable | TBRegisterReadable::Yes |
| Writable | TBRegisterWritable::Yes |
| Short Description | ShortDesc::Pi I2S clock divide in master mode. |
bits 7:0 = Clock divide sets sample rate when in master mode (soft reset = decimal 11)
clock divider = 538461 / SampleRateHz - 1
The default value corresponds to 48952Hz sample rate.