Video Modes - Revision history

SevenFFF: Fixed lores pixel address ranges

2025-01-14T18:38:58Z

Fixed lores pixel address ranges

← Older revision		Revision as of 19:38, 14 January 2025
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	LoRes layer is enabled by setting bit 7 in {{NextRegNo\|$15}}. The number of available colours is selected by bit 5 in {{NextRegNo\|$6A}} with 0 selecting 256 colours and 1 selecting 16 colours.		LoRes layer is enabled by setting bit 7 in {{NextRegNo\|$15}}. The number of available colours is selected by bit 5 in {{NextRegNo\|$6A}} with 0 selecting 256 colours and 1 selecting 16 colours.

	In 256 colour mode each pixel is assigned one byte, in reading order (without interleaving). The first 48 lines are stored between $4000 and $~~5800~~ (16K bank 5 $0000-$~~1800~~), and the second 48 between $6000 and $~~7800~~ (16k bank 5 $2000-$~~3800~~). Each byte is an index into the ULA palette.		In 256 colour mode each pixel is assigned one byte, in reading order (without interleaving). The first 48 lines are stored between $4000 and $57ff (16K bank 5 $0000-$17ff), and the second 48 between $6000 and $77ff (16k bank 5 $2000-$37ff). Each byte is an index into the ULA palette.

	In 16 colour mode a byte corresponds to a pair of pixels with the most significant nybble corresponding to the left pixel and the least significant to the right pixel. Pixels are arranged in memory in reading order (without interleaving). The image is stored in one of two locations either $4000-$~~5800~~ (16K bank 5 $0000-$~~1800~~) or $6000-$~~7800~~ (16K bank 5 $2000-$~~3800~~). The location is determined by the xor of bit 4 of {{NextRegNo\|$6A}} and bit 0 of {{PortNo\|$xxFF}}. The colour of each pixel combines the value of its corresponding nybble with the Radistan palette offset in bits 3-0 of {{NextRegNo\|$6A}}.		In 16 colour mode a byte corresponds to a pair of pixels with the most significant nybble corresponding to the left pixel and the least significant to the right pixel. Pixels are arranged in memory in reading order (without interleaving). The image is stored in one of two locations either $4000-$57ff (16K bank 5 $0000-$17ff) or $6000-$77ff (16K bank 5 $2000-$37ff). The location is determined by the xor of bit 4 of {{NextRegNo\|$6A}} and bit 0 of {{PortNo\|$xxFF}}. The colour of each pixel combines the value of its corresponding nybble with the Radistan palette offset in bits 3-0 of {{NextRegNo\|$6A}}.

	== Enhanced ULA ==		== Enhanced ULA ==

Varmfskii: Added info on the 16 colour lores mode

2020-11-19T14:42:30Z

Added info on the 16 colour lores mode

← Older revision		Revision as of 15:42, 19 November 2020
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	== LoRes Layer/Radasjimian Mode ==		== LoRes Layer/Radasjimian Mode ==
	LoRes Layer is a mode similar to the "Radastanian Mode" on the ZXUno, in that it offers reduced resolution in exchange for more colors. LoRes Layer ~~allows~~ any of 256 colors anywhere on the screen, but lowers the resolution in both dimensions to 128x96.		LoRes Layer is a mode similar to the "Radastanian Mode" on the ZXUno, in that it offers reduced resolution in exchange for more colors. LoRes Layer has two submodes allowing any of either 16 or 256 colors anywhere on the screen, but lowers the resolution in both dimensions to 128x96.

	LoRes layer is enabled by setting bit 7 in {{NextRegNo\|$15}}. ~~Each~~ pixel is assigned one byte, in reading order (without interleaving). The first 48 lines are stored between $4000 and $5800, and the second 48 between $6000 and $7800. Each byte is an index into the ULA palette.		LoRes layer is enabled by setting bit 7 in {{NextRegNo\|$15}}. The number of available colours is selected by bit 5 in {{NextRegNo\|$6A}} with 0 selecting 256 colours and 1 selecting 16 colours.

			In 256 colour mode each pixel is assigned one byte, in reading order (without interleaving). The first 48 lines are stored between $4000 and $5800 (16K bank 5 $0000-$1800), and the second 48 between $6000 and $7800 (16k bank 5 $2000-$3800). Each byte is an index into the ULA palette.

			In 16 colour mode a byte corresponds to a pair of pixels with the most significant nybble corresponding to the left pixel and the least significant to the right pixel. Pixels are arranged in memory in reading order (without interleaving). The image is stored in one of two locations either $4000-$5800 (16K bank 5 $0000-$1800) or $6000-$7800 (16K bank 5 $2000-$3800). The location is determined by the xor of bit 4 of {{NextRegNo\|$6A}} and bit 0 of {{PortNo\|$xxFF}}. The colour of each pixel combines the value of its corresponding nybble with the Radistan palette offset in bits 3-0 of {{NextRegNo\|$6A}}.

	== Enhanced ULA ==		== Enhanced ULA ==

Ped7g: core 3.0 changes/refresh

2019-12-31T10:10:16Z

core 3.0 changes/refresh

← Older revision		Revision as of 11:10, 31 December 2019
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	== Timex Sinclair Double Buffering ==		== Timex Sinclair Double Buffering ==
	Writing %001 to the lower 3 bits of {{PortNo\|$xxFF}} will change the accessed base screen address to $6000 instead of $4000 (or otherwise add $2000 to the accessed true address, moving it into the second half of the appropriate 16k-bank or the next 8k-bank). Writing %000 restores the normal base screen address. This allows this area of memory to be used for a "double buffer" for smooth frame transitions. Note however that the Spectrum 128k's bank switching also allows double buffering (see [[Memory map]]) ~~which~~ can ~~be combined with this - although the 128K modes CANNOT~~ be used ~~with Layer 2 due to sharing~~ BRAM in the FPGA.		Writing %001 to the lower 3 bits of {{PortNo\|$xxFF}} will change the accessed base screen address to $6000 instead of $4000 (or otherwise add $2000 to the accessed true address, moving it into the second half of the appropriate 16k-bank or the next 8k-bank). Writing %000 restores the normal base screen address. This allows this area of memory to be used for a "double buffer" for smooth frame transitions. Note however that the Spectrum 128k's bank switching also allows double buffering (using Bank 7, see [[Memory map]]), but only first half of bank 7 is mirrored inside the FPGA in the fast BRAM region. The Layer 2 can be used in parallel only when ULA layer data are coming from BRAM memory in the FPGA (the mirror of first half of Bank 7 is new feature of latest cores 3.0.x, in 2.0 cores using the ZX128 shadow screen caused the Layer 2 to switch off).

	== Timex Sinclair Hi-Res Mode ==		== Timex Sinclair Hi-Res Mode ==
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	The Spectrum Next comes with Enhanced ULA which allows the standard Spectrum graphics to display 256 colours on the screen at once. It uses the system [[Palettes]] in the same way as [[Sprites]] and [[Layer 2]].		The Spectrum Next comes with Enhanced ULA which allows the standard Spectrum graphics to display 256 colours on the screen at once. It uses the system [[Palettes]] in the same way as [[Sprites]] and [[Layer 2]].

	Setting bit 0 of {{NextRegNo\|$43}} enables the Enhanced ULA mode. In this mode, the breakdown of Ink/Paper/FLASH/BRIGHT bits in the attribute cells given above is ignored. Instead, the bit value written to {{NextRegNo\|$42}} is used as a bitmask to determine which bits are used for the ink color palette index (it must mask off a number of bits on the LSB side, eg %00111111, so not %01010101 or anything silly like that!) and the remaining bits, with 128 added, are used for the paper color palette index. The mask %11111111, to treat ''all'' bits as ink, is legal; if used the paper color in every cell will be color 128. The mask %00000000 to treat all bits as paper is not legal.		Setting bit 0 of {{NextRegNo\|$43}} enables the Enhanced ULA mode. In this mode, the breakdown of Ink/Paper/FLASH/BRIGHT bits in the attribute cells given above is ignored. Instead, the bit value written to {{NextRegNo\|$42}} is used as a bitmask to determine which bits are used for the ink color palette index (it must mask off a number of bits on the LSB side, eg %00111111, so not %01010101 or anything silly like that!) and the remaining bits, with 128 added, are used for the paper color palette index. The mask %11111111, to treat ''all'' bits as ink, is legal; if used the paper color in every cell will be {{NextRegNo\|$4A}} (since core 3.0, it was color index 128 in 2.0 core). The mask %00000000 to treat all bits as paper is not legal.

	= Additional features =		= Additional features =
	In addition to the Enhanced ULA, the Spectrum Next adds [[Sprites]], [[Layer 2]] and a [[Tilemap]] which are not ULA controlled.		In addition to the Enhanced ULA, the Spectrum Next adds [[Sprites]], [[Layer 2]] and a [[Tilemap]] which are not ULA controlled.

Julian S at 18:53, 3 May 2019

2019-05-03T18:53:29Z

← Older revision		Revision as of 19:53, 3 May 2019
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	== Timex Sinclair Double Buffering ==		== Timex Sinclair Double Buffering ==
	Writing %001 to the lower 3 bits of {{PortNo\|$xxFF}} will change the accessed base screen address to $6000 instead of $4000 (or otherwise add $2000 to the accessed true address, moving it into the second half of the appropriate 16k-bank or the next 8k-bank). Writing %000 restores the normal base screen address. This allows this area of memory to be used for a "double buffer" for smooth frame transitions. Note however that the Spectrum 128k's bank switching also allows double buffering (see [[Memory map]]) which can be combined with this - although the 128K modes CANNOT be used with ~~Layer2~~ due to sharing BRAM in the FPGA.		Writing %001 to the lower 3 bits of {{PortNo\|$xxFF}} will change the accessed base screen address to $6000 instead of $4000 (or otherwise add $2000 to the accessed true address, moving it into the second half of the appropriate 16k-bank or the next 8k-bank). Writing %000 restores the normal base screen address. This allows this area of memory to be used for a "double buffer" for smooth frame transitions. Note however that the Spectrum 128k's bank switching also allows double buffering (see [[Memory map]]) which can be combined with this - although the 128K modes CANNOT be used with Layer 2 due to sharing BRAM in the FPGA.

	== Timex Sinclair Hi-Res Mode ==		== Timex Sinclair Hi-Res Mode ==
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	The Spectrum Next comes with Enhanced ULA which allows the standard Spectrum graphics to display 256 colours on the screen at once. It uses the system [[Palettes]] in the same way as [[Sprites]] and [[Layer 2]].		The Spectrum Next comes with Enhanced ULA which allows the standard Spectrum graphics to display 256 colours on the screen at once. It uses the system [[Palettes]] in the same way as [[Sprites]] and [[Layer 2]].

	Setting bit 0 of {{NextRegNo\|$43}} enables the Enhanced ULA mode. In this mode the breakdown of Ink/Paper/FLASH/BRIGHT bits in the attribute cells given above is ignored. Instead, the bit value written to {{NextRegNo\|$42}} is used as a bitmask to determine which bits are used for the ink color palette index (it must mask off a number of bits on the LSB side, eg %00111111, so not %01010101 or anything silly like that!) and the remaining bits, with 128 added, are used for the paper color palette index. The mask %11111111, to treat ''all'' bits as ink, is legal; if used the paper color in every cell will be color 128. The mask %00000000 to treat all bits as paper is not legal.		Setting bit 0 of {{NextRegNo\|$43}} enables the Enhanced ULA mode. In this mode, the breakdown of Ink/Paper/FLASH/BRIGHT bits in the attribute cells given above is ignored. Instead, the bit value written to {{NextRegNo\|$42}} is used as a bitmask to determine which bits are used for the ink color palette index (it must mask off a number of bits on the LSB side, eg %00111111, so not %01010101 or anything silly like that!) and the remaining bits, with 128 added, are used for the paper color palette index. The mask %11111111, to treat ''all'' bits as ink, is legal; if used the paper color in every cell will be color 128. The mask %00000000 to treat all bits as paper is not legal.

	= Additional features =		= Additional features =
	In addition to the Enhanced ULA, the Spectrum Next adds [[Sprites]], [[Layer 2]] and a [[Tilemap]] which are not ULA controlled.		In addition to the Enhanced ULA, the Spectrum Next adds [[Sprites]], [[Layer 2]] and a [[Tilemap]] which are not ULA controlled.

Mikecad: Mikecad moved page Enhanced ULA to Video Modes without leaving a redirect

2019-04-20T12:50:48Z

Mikecad moved page Enhanced ULA to Video Modes without leaving a redirect

← Older revision	Revision as of 13:50, 20 April 2019
(No difference)

Mikecad at 12:07, 20 April 2019

2019-04-20T12:07:45Z

← Older revision		Revision as of 13:07, 20 April 2019
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	The ULA is the Spectrum video and input chip. The ~~enhanced~~ ULA adds extra video modes and features to the standard Spectrum.		The ULA is the Spectrum video and input chip. The Enhanced ULA adds extra video modes and features to the standard Spectrum.

	ULA stands for "Uncommitted Logic Array" and refers to the manufacturing process involved. It does not relate to the video behavior of the chip. The chip itself is a custom chip.		ULA stands for "Uncommitted Logic Array" and refers to the manufacturing process involved. It does not relate to the video behavior of the chip. The chip itself is a custom chip.
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	\|}		\|}

	If ~~ULANext~~ is enabled, then this no longer applies; see below.		If Enhanced ULA is enabled, then this no longer applies; see below.

	== Calculating line addresses in interleaved video modes ==		== Calculating line addresses in interleaved video modes ==
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	LoRes layer is enabled by setting bit 7 in {{NextRegNo\|$15}}. Each pixel is assigned one byte, in reading order (without interleaving). The first 48 lines are stored between $4000 and $5800, and the second 48 between $6000 and $7800. Each byte is an index into the ULA palette.		LoRes layer is enabled by setting bit 7 in {{NextRegNo\|$15}}. Each pixel is assigned one byte, in reading order (without interleaving). The first 48 lines are stored between $4000 and $5800, and the second 48 between $6000 and $7800. Each byte is an index into the ULA palette.

	== ~~ULANext~~ ==		== Enhanced ULA ==

	The Spectrum Next comes with ~~an enhanced~~ ULA ~~called ULANext~~ which allows the standard Spectrum graphics to display 256 colours on the screen at once. It uses the system [[Palettes]] in the same way as [[Sprites]] and [[Layer 2]].		The Spectrum Next comes with Enhanced ULA which allows the standard Spectrum graphics to display 256 colours on the screen at once. It uses the system [[Palettes]] in the same way as [[Sprites]] and [[Layer 2]].

	Setting bit 0 of {{NextRegNo\|$43}} enables the ~~ULANext~~ mode. In this mode the breakdown of Ink/Paper/FLASH/BRIGHT bits in the attribute cells given above is ignored. Instead, the bit value written to {{NextRegNo\|$42}} is used as a bitmask to determine which bits are used for the ink color palette index (it must mask off a number of bits on the LSB side, eg %00111111, so not %01010101 or anything silly like that!) and the remaining bits, with 128 added, are used for the paper color palette index. The mask %11111111, to treat ''all'' bits as ink, is legal; if used the paper color in every cell will be color 128. The mask %00000000 to treat all bits as paper is not legal.		Setting bit 0 of {{NextRegNo\|$43}} enables the Enhanced ULA mode. In this mode the breakdown of Ink/Paper/FLASH/BRIGHT bits in the attribute cells given above is ignored. Instead, the bit value written to {{NextRegNo\|$42}} is used as a bitmask to determine which bits are used for the ink color palette index (it must mask off a number of bits on the LSB side, eg %00111111, so not %01010101 or anything silly like that!) and the remaining bits, with 128 added, are used for the paper color palette index. The mask %11111111, to treat ''all'' bits as ink, is legal; if used the paper color in every cell will be color 128. The mask %00000000 to treat all bits as paper is not legal.

	= Additional features =		= Additional features =
	In addition to the Enhanced ULA, the Spectrum Next adds [[Sprites]], [[Layer 2]] and a [[Tilemap]] which are not ULA controlled.		In addition to the Enhanced ULA, the Spectrum Next adds [[Sprites]], [[Layer 2]] and a [[Tilemap]] which are not ULA controlled.

Specnext: 36 revisions imported

2019-04-14T09:59:53Z

36 revisions imported

← Older revision	Revision as of 10:59, 14 April 2019
(No difference)

wiki>Varmfskii: /* Additional features */

2019-03-06T00:16:00Z

Additional features

← Older revision		Revision as of 01:16, 6 March 2019
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	= Additional features =		= Additional features =
	In addition to the Enhanced ULA, the Spectrum Next adds [[Sprites]] ~~and~~ [[Layer 2]] which are not ULA controlled.		In addition to the Enhanced ULA, the Spectrum Next adds [[Sprites]], [[Layer 2]] and a [[Tilemap]] which are not ULA controlled.

wiki>Ped7g at 02:16, 23 December 2018

2018-12-23T02:16:58Z

← Older revision		Revision as of 03:16, 23 December 2018
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	== Timex Sinclair Hi-Res Mode ==		== Timex Sinclair Hi-Res Mode ==
	Writing %110 to the lower 3 bits of {{PortNo\|$xxFF}} will change the screen resolution to 512x192, doubling the X resolution. This still uses the Double Buffer structure of one set of screen data at $4000 and another at $6000, but now columns are alternately read from the two buffers to account for the higher resolution. In addition, attributes are disabled: this mode supports only two colors. Which they are can be set by writing bits 3-5 of {{PortNo\|$xxFF}}.		Writing %110 to the lower 3 bits of {{PortNo\|$xxFF}} will change the screen resolution to 512x192, doubling the X resolution. This still uses the Double Buffer structure of one set of screen data at $4000 and another at $6000, but now columns (one column = one byte = 8 pixels) are alternately read from the two buffers to account for the higher resolution. In addition, attributes are disabled: this mode supports only two colors. Which they are can be set by writing bits 3-5 of {{PortNo\|$xxFF}}.

	== Timex Sinclair Hi-Color Mode ==		== Timex Sinclair Hi-Color Mode ==

wiki>Timbucus at 22:52, 18 August 2018

2018-08-18T22:52:05Z

← Older revision		Revision as of 23:52, 18 August 2018
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	== Timex Sinclair Double Buffering ==		== Timex Sinclair Double Buffering ==
	Writing %001 to the lower 3 bits of {{PortNo\|$xxFF}} will change the accessed base screen address to $6000 instead of $4000 (or otherwise add $2000 to the accessed true address, moving it into the second half of the appropriate 16k-bank or the next 8k-bank). Writing %000 restores the normal base screen address. This allows this area of memory to be used for a "double buffer" for smooth frame transitions. Note however that the Spectrum 128k's bank switching also allows double buffering (see [[Memory map]]) which can be combined with this.		Writing %001 to the lower 3 bits of {{PortNo\|$xxFF}} will change the accessed base screen address to $6000 instead of $4000 (or otherwise add $2000 to the accessed true address, moving it into the second half of the appropriate 16k-bank or the next 8k-bank). Writing %000 restores the normal base screen address. This allows this area of memory to be used for a "double buffer" for smooth frame transitions. Note however that the Spectrum 128k's bank switching also allows double buffering (see [[Memory map]]) which can be combined with this - although the 128K modes CANNOT be used with Layer2 due to sharing BRAM in the FPGA.

	== Timex Sinclair Hi-Res Mode ==		== Timex Sinclair Hi-Res Mode ==
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	== ULANext ==		== ULANext ==

	The Spectrum Next comes with an enhanced ULA called ULANext which allows the standard Spectrum graphics to display 256 ~~colors~~ on the screen at once. It uses the system [[Palettes]] in the same way as [[Sprites]] and [[Layer 2]].		The Spectrum Next comes with an enhanced ULA called ULANext which allows the standard Spectrum graphics to display 256 colours on the screen at once. It uses the system [[Palettes]] in the same way as [[Sprites]] and [[Layer 2]].

	Setting bit 0 of {{NextRegNo\|$43}} enables the ULANext mode. In this mode the breakdown of Ink/Paper/FLASH/BRIGHT bits in the attribute cells given above is ignored. Instead, the bit value written to {{NextRegNo\|$42}} is used as a bitmask to determine which bits are used for the ink color palette index (it must mask off a number of bits on the LSB side, eg %00111111, so not %01010101 or anything silly like that!) and the remaining bits, with 128 added, are used for the paper color palette index. The mask %11111111, to treat ''all'' bits as ink, is legal; if used the paper color in every cell will be color 128. The mask %00000000 to treat all bits as paper is not legal.		Setting bit 0 of {{NextRegNo\|$43}} enables the ULANext mode. In this mode the breakdown of Ink/Paper/FLASH/BRIGHT bits in the attribute cells given above is ignored. Instead, the bit value written to {{NextRegNo\|$42}} is used as a bitmask to determine which bits are used for the ink color palette index (it must mask off a number of bits on the LSB side, eg %00111111, so not %01010101 or anything silly like that!) and the remaining bits, with 128 added, are used for the paper color palette index. The mask %11111111, to treat ''all'' bits as ink, is legal; if used the paper color in every cell will be color 128. The mask %00000000 to treat all bits as paper is not legal.