Memory map - Revision history

Johnnyo: port 123B manually relinked

2025-12-05T16:42:42Z

port 123B manually relinked

← Older revision		Revision as of 17:42, 5 December 2025
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	=== Layer 2 Switching ===		=== Layer 2 Switching ===
	Layer 2 switching can allow one of the 16k-banks to be ''written to'' or ''read from'' in 16k-slot 1, by writing the 16k-bank number to {{NextRegNo\|$12}} and then enabling Layer 2 paging by setting the paging bits in ~~{{PortNo~~\|$123B}}. You can use also the {{NextRegNo\|$13}} for the same purpose (change of register $12 is immediately visible at display, while register $13 is not related to display in any way, it works only as bank selector for writing into slot 1). Since core 3.0 you can page not only first 16kiB, but whole 48kiB of Layer 2 to address region $0000..$BFFF).		Layer 2 switching can allow one of the 16k-banks to be ''written to'' or ''read from'' in 16k-slot 1, by writing the 16k-bank number to {{NextRegNo\|$12}} and then enabling Layer 2 paging by setting the paging bits in [[Layer_2_Access_Port \| Port $123B]]. You can use also the {{NextRegNo\|$13}} for the same purpose (change of register $12 is immediately visible at display, while register $13 is not related to display in any way, it works only as bank selector for writing into slot 1). Since core 3.0 you can page not only first 16kiB, but whole 48kiB of Layer 2 to address region $0000..$BFFF).

	Writing to/reading from this paging area will then write/read the appropriate area of memory, whereas the other operation may remain unaffected and use the area mapped by other memory management.		Writing to/reading from this paging area will then write/read the appropriate area of memory, whereas the other operation may remain unaffected and use the area mapped by other memory management.

Johnnyo: fix 1FFD links

2025-12-05T16:37:59Z

fix 1FFD links

← Older revision		Revision as of 17:37, 5 December 2025
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	On an unexpanded Next, this allows any 16k-bank to be paged in at $c000. On an expanded Next, there are not enough bits available to access the banks at the bottom of the expanded memory, so Next memory management must be used to access these.		On an unexpanded Next, this allows any 16k-bank to be paged in at $c000. On an expanded Next, there are not enough bits available to access the banks at the bottom of the expanded memory, so Next memory management must be used to access these.

	If you are using the standard interrupt handler or OS routines, then any time you write to [[Memory_Paging_Control \| Port $7FFD]] you should also store the value at $5B5C. Any time you write to [Plus_3_Memory_Paging_Control \| Port $1FFD]] you should also store the value at $5B67. There is no corresponding system variable for the Next-only [[Next_Memory_Bank_Select \| Port $DFFD]] and standard OS routines may not support the extended banks properly.		If you are using the standard interrupt handler or OS routines, then any time you write to [[Memory_Paging_Control \| Port $7FFD]] you should also store the value at $5B5C. Any time you write to [[Plus_3_Memory_Paging_Control \| Port $1FFD]] you should also store the value at $5B67. There is no corresponding system variable for the Next-only [[Next_Memory_Bank_Select \| Port $DFFD]] and standard OS routines may not support the extended banks properly.

	=== 128 Special Paging Mode ===		=== 128 Special Paging Mode ===
	"Special paging mode" (also called "AllRam mode" or "CP/M mode") is enabled by writing a value with the LSB set to [Plus_3_Memory_Paging_Control \| Port $1FFD]]. Depending on the 3 low bits of this value a memory configuration is selected as follows:		"Special paging mode" (also called "AllRam mode" or "CP/M mode") is enabled by writing a value with the LSB set to [[Plus_3_Memory_Paging_Control \| Port $1FFD]]. Depending on the 3 low bits of this value a memory configuration is selected as follows:
	{\| class="wikitable"		{\| class="wikitable"
	! Bits !! Slot 1 !! Slot 2 !! Slot 3 \|\| Slot 4		! Bits !! Slot 1 !! Slot 2 !! Slot 3 \|\| Slot 4
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	$0000-$3fff is usually mapped to ROM. This area can only be fully remapped using Next memory management. ROM is not considered one of the numbered banks; it is mapped to the two 8k-banks by default, or by setting their 8k-bank numbers to 255.		$0000-$3fff is usually mapped to ROM. This area can only be fully remapped using Next memory management. ROM is not considered one of the numbered banks; it is mapped to the two 8k-banks by default, or by setting their 8k-bank numbers to 255.

	The 128k Spectrum has 2 ROM pages. Which of these is mapped is selected by altering Bit 4 of [[Memory_Paging_Control \| Port $7FFD]]. The +2a/+3 has 4 ROM pages; the extra bit needed to select between these is bit 2 of [Plus_3_Memory_Paging_Control \| Port $1FFD]]. This maintains compatibility with the original machines' ROM paging as long as the ROM is not paged out.		The 128k Spectrum has 2 ROM pages. Which of these is mapped is selected by altering Bit 4 of [[Memory_Paging_Control \| Port $7FFD]]. The +2a/+3 has 4 ROM pages; the extra bit needed to select between these is bit 2 of [[Plus_3_Memory_Paging_Control \| Port $1FFD]]. This maintains compatibility with the original machines' ROM paging as long as the ROM is not paged out.

	=== Paging out ROM ===		=== Paging out ROM ===

Johnnyo: port 1FFD manually relinked

2025-12-05T16:36:50Z

port 1FFD manually relinked

← Older revision		Revision as of 17:36, 5 December 2025
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	On an unexpanded Next, this allows any 16k-bank to be paged in at $c000. On an expanded Next, there are not enough bits available to access the banks at the bottom of the expanded memory, so Next memory management must be used to access these.		On an unexpanded Next, this allows any 16k-bank to be paged in at $c000. On an expanded Next, there are not enough bits available to access the banks at the bottom of the expanded memory, so Next memory management must be used to access these.

	If you are using the standard interrupt handler or OS routines, then any time you write to [[Memory_Paging_Control \| Port $7FFD]] you should also store the value at $5B5C. Any time you write to ~~{{PortNo~~\|$1FFD}} you should also store the value at $5B67. There is no corresponding system variable for the Next-only [[Next_Memory_Bank_Select \| Port $DFFD]] and standard OS routines may not support the extended banks properly.		If you are using the standard interrupt handler or OS routines, then any time you write to [[Memory_Paging_Control \| Port $7FFD]] you should also store the value at $5B5C. Any time you write to [Plus_3_Memory_Paging_Control \| Port $1FFD]] you should also store the value at $5B67. There is no corresponding system variable for the Next-only [[Next_Memory_Bank_Select \| Port $DFFD]] and standard OS routines may not support the extended banks properly.

	=== 128 Special Paging Mode ===		=== 128 Special Paging Mode ===
	"Special paging mode" (also called "AllRam mode" or "CP/M mode") is enabled by writing a value with the LSB set to ~~{{PortNo~~\|$1FFD}}. Depending on the 3 low bits of this value a memory configuration is selected as follows:		"Special paging mode" (also called "AllRam mode" or "CP/M mode") is enabled by writing a value with the LSB set to [Plus_3_Memory_Paging_Control \| Port $1FFD]]. Depending on the 3 low bits of this value a memory configuration is selected as follows:
	{\| class="wikitable"		{\| class="wikitable"
	! Bits !! Slot 1 !! Slot 2 !! Slot 3 \|\| Slot 4		! Bits !! Slot 1 !! Slot 2 !! Slot 3 \|\| Slot 4
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	$0000-$3fff is usually mapped to ROM. This area can only be fully remapped using Next memory management. ROM is not considered one of the numbered banks; it is mapped to the two 8k-banks by default, or by setting their 8k-bank numbers to 255.		$0000-$3fff is usually mapped to ROM. This area can only be fully remapped using Next memory management. ROM is not considered one of the numbered banks; it is mapped to the two 8k-banks by default, or by setting their 8k-bank numbers to 255.

	The 128k Spectrum has 2 ROM pages. Which of these is mapped is selected by altering Bit 4 of [[Memory_Paging_Control \| Port $7FFD]]. The +2a/+3 has 4 ROM pages; the extra bit needed to select between these is bit 2 of ~~{{PortNo~~\|$1FFD}}. This maintains compatibility with the original machines' ROM paging as long as the ROM is not paged out.		The 128k Spectrum has 2 ROM pages. Which of these is mapped is selected by altering Bit 4 of [[Memory_Paging_Control \| Port $7FFD]]. The +2a/+3 has 4 ROM pages; the extra bit needed to select between these is bit 2 of [Plus_3_Memory_Paging_Control \| Port $1FFD]]. This maintains compatibility with the original machines' ROM paging as long as the ROM is not paged out.

	=== Paging out ROM ===		=== Paging out ROM ===

Johnnyo: port DFFD manually relinked

2025-12-05T16:34:23Z

port DFFD manually relinked

← Older revision		Revision as of 17:34, 5 December 2025
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	=== 128-style memory management ===		=== 128-style memory management ===

	128-style memory management can only alter the bank addressed at $c000 (16k-slot 4, or 8k-slot 7-8). The active 16k-bank at $c000 is selected by writing the 3 LSBs of the 16k-bank number to the bottom 3 bits of [[Memory_Paging_Control \| Port $7FFD]], and the 3 MSBs to the bottom 3 bits of ~~{{PortNo~~\|$DFFD}}. (The reason for the division is that the original Spectrum 128, having only 128k of memory, only needed 3 bits.)		128-style memory management can only alter the bank addressed at $c000 (16k-slot 4, or 8k-slot 7-8). The active 16k-bank at $c000 is selected by writing the 3 LSBs of the 16k-bank number to the bottom 3 bits of [[Memory_Paging_Control \| Port $7FFD]], and the 3 MSBs to the bottom 3 bits of [[Next_Memory_Bank_Select \| Port $DFFD]]. (The reason for the division is that the original Spectrum 128, having only 128k of memory, only needed 3 bits.)

	On an unexpanded Next, this allows any 16k-bank to be paged in at $c000. On an expanded Next, there are not enough bits available to access the banks at the bottom of the expanded memory, so Next memory management must be used to access these.		On an unexpanded Next, this allows any 16k-bank to be paged in at $c000. On an expanded Next, there are not enough bits available to access the banks at the bottom of the expanded memory, so Next memory management must be used to access these.

	If you are using the standard interrupt handler or OS routines, then any time you write to [[Memory_Paging_Control \| Port $7FFD]] you should also store the value at $5B5C. Any time you write to {{PortNo\|$1FFD}} you should also store the value at $5B67. There is no corresponding system variable for the Next-only ~~{{PortNo~~\|$DFFD}} and standard OS routines may not support the extended banks properly.		If you are using the standard interrupt handler or OS routines, then any time you write to [[Memory_Paging_Control \| Port $7FFD]] you should also store the value at $5B5C. Any time you write to {{PortNo\|$1FFD}} you should also store the value at $5B67. There is no corresponding system variable for the Next-only [[Next_Memory_Bank_Select \| Port $DFFD]] and standard OS routines may not support the extended banks properly.

	=== 128 Special Paging Mode ===		=== 128 Special Paging Mode ===

Johnnyo at 16:31, 5 December 2025

2025-12-05T16:31:20Z

← Older revision		Revision as of 17:31, 5 December 2025
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	=== 128-style memory management ===		=== 128-style memory management ===

	128-style memory management can only alter the bank addressed at $c000 (16k-slot 4, or 8k-slot 7-8). The active 16k-bank at $c000 is selected by writing the 3 LSBs of the 16k-bank number to the bottom 3 bits of ~~{{PortNo~~\|$7FFD}}, and the 3 MSBs to the bottom 3 bits of {{PortNo\|$DFFD}}. (The reason for the division is that the original Spectrum 128, having only 128k of memory, only needed 3 bits.)		128-style memory management can only alter the bank addressed at $c000 (16k-slot 4, or 8k-slot 7-8). The active 16k-bank at $c000 is selected by writing the 3 LSBs of the 16k-bank number to the bottom 3 bits of [[Memory_Paging_Control \| Port $7FFD]], and the 3 MSBs to the bottom 3 bits of {{PortNo\|$DFFD}}. (The reason for the division is that the original Spectrum 128, having only 128k of memory, only needed 3 bits.)

	On an unexpanded Next, this allows any 16k-bank to be paged in at $c000. On an expanded Next, there are not enough bits available to access the banks at the bottom of the expanded memory, so Next memory management must be used to access these.		On an unexpanded Next, this allows any 16k-bank to be paged in at $c000. On an expanded Next, there are not enough bits available to access the banks at the bottom of the expanded memory, so Next memory management must be used to access these.

	If you are using the standard interrupt handler or OS routines, then any time you write to ~~{{PortNo~~\|$7FFD}} you should also store the value at $5B5C. Any time you write to {{PortNo\|$1FFD}} you should also store the value at $5B67. There is no corresponding system variable for the Next-only {{PortNo\|$DFFD}} and standard OS routines may not support the extended banks properly.		If you are using the standard interrupt handler or OS routines, then any time you write to [[Memory_Paging_Control \| Port $7FFD]] you should also store the value at $5B5C. Any time you write to {{PortNo\|$1FFD}} you should also store the value at $5B67. There is no corresponding system variable for the Next-only {{PortNo\|$DFFD}} and standard OS routines may not support the extended banks properly.

	=== 128 Special Paging Mode ===		=== 128 Special Paging Mode ===
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	$0000-$3fff is usually mapped to ROM. This area can only be fully remapped using Next memory management. ROM is not considered one of the numbered banks; it is mapped to the two 8k-banks by default, or by setting their 8k-bank numbers to 255.		$0000-$3fff is usually mapped to ROM. This area can only be fully remapped using Next memory management. ROM is not considered one of the numbered banks; it is mapped to the two 8k-banks by default, or by setting their 8k-bank numbers to 255.

	The 128k Spectrum has 2 ROM pages. Which of these is mapped is selected by altering Bit 4 of ~~{{PortNo~~\|$7FFD}}. The +2a/+3 has 4 ROM pages; the extra bit needed to select between these is bit 2 of {{PortNo\|$1FFD}}. This maintains compatibility with the original machines' ROM paging as long as the ROM is not paged out.		The 128k Spectrum has 2 ROM pages. Which of these is mapped is selected by altering Bit 4 of [[Memory_Paging_Control \| Port $7FFD]]. The +2a/+3 has 4 ROM pages; the extra bit needed to select between these is bit 2 of {{PortNo\|$1FFD}}. This maintains compatibility with the original machines' ROM paging as long as the ROM is not paged out.

	=== Paging out ROM ===		=== Paging out ROM ===
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	== Screen ==		== Screen ==
	16k-Bank 5 is the bank read by the ULA to determine what to show on screen. The ULA connects directly to the larger memory space ignoring mapping; the screen is always 16k-Bank 5, no matter where in memory it is (or if it is switched in at all). Setting bit 3 of ~~{{PortNo~~\|$7FFD}} will have the ULA read from 16k-bank 7 (the "shadow screen") instead, which can be used as an alternate screen. Beware that '''this does not map 16k-bank 7 into RAM'''; to alter 16k-bank 7 it must be mapped by other means.		16k-Bank 5 is the bank read by the ULA to determine what to show on screen. The ULA connects directly to the larger memory space ignoring mapping; the screen is always 16k-Bank 5, no matter where in memory it is (or if it is switched in at all). Setting bit 3 of [[Memory_Paging_Control \| Port $7FFD]] will have the ULA read from 16k-bank 7 (the "shadow screen") instead, which can be used as an alternate screen. Beware that '''this does not map 16k-bank 7 into RAM'''; to alter 16k-bank 7 it must be mapped by other means.

Johnnyo: /* Memory decoding order */

2025-12-04T19:03:03Z

Memory decoding order

← Older revision		Revision as of 20:03, 4 December 2025
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	Accesses to (the RAM of 16KB) "bank 5" or (the first 8KB RAM of the RAM of 16KB) "bank 7" always go to internal bram with the following three exceptions:		Accesses to (the RAM of 16KB) "bank 5" or (the first 8KB RAM of the RAM of 16KB) "bank 7" always go to internal bram with the following three exceptions:

	1 ''Layer 2 itself has a direct connection to external sram'' so while (the core is) reading bytes to generate video, all bytes read (for Layer 2) come from external sram. It has no connection to internal bram so its "bank 5" or "bank 7" accesses are from external sram and not internal bram.		1 ''Layer 2 itself has a direct connection to external sram'' so while (the core is) reading bytes to generate video, all bytes read (for Layer 2) come from external sram. It (Layer 2) has no connection to internal bram so its "bank 5" or "bank 7" accesses are from external sram and not internal bram.

	2 ''Layer 2 mapping is a mapping to external sram only.'' So (in the context of Layer 2 mapping) "bank 5" or "bank 7" will not come from internal bram but from external sram which is how the cpu can uncover that otherwise hidden memory in external sram.		2 ''Layer 2 mapping is a mapping to external sram only.'' So (in the context of Layer 2 mapping) "bank 5" or "bank 7" will not come from internal bram but from external sram which is how the cpu can uncover that otherwise hidden memory in external sram.

Johnnyo: /* Memory decoding order */

2025-12-04T17:40:24Z

Memory decoding order

← Older revision		Revision as of 18:40, 4 December 2025
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	Accesses to (the RAM of 16KB) "bank 5" or (the first 8KB RAM of the RAM of 16KB) "bank 7" always go to internal bram with the following three exceptions:		Accesses to (the RAM of 16KB) "bank 5" or (the first 8KB RAM of the RAM of 16KB) "bank 7" always go to internal bram with the following three exceptions:

	1 Layer 2 itself has a direct connection to external sram so while (the core is) reading bytes to generate video, all bytes read come from external sram. It has no connection to internal bram so its "bank 5" or "bank 7" accesses are from external sram and not internal bram.		1 ''Layer 2 itself has a direct connection to external sram'' so while (the core is) reading bytes to generate video, all bytes read (for Layer 2) come from external sram. It has no connection to internal bram so its "bank 5" or "bank 7" accesses are from external sram and not internal bram.

	2 Layer 2 mapping is a mapping to external sram only. So "bank 5" or "bank 7" will not come from internal bram but from external sram which is how the cpu can uncover that otherwise hidden memory in external sram.		2 ''Layer 2 mapping is a mapping to external sram only.'' So (in the context of Layer 2 mapping) "bank 5" or "bank 7" will not come from internal bram but from external sram which is how the cpu can uncover that otherwise hidden memory in external sram.

	3 The config mapping is also an external sram mapping.		3 The config mapping is also an external sram mapping.

Johnnyo: /* Memory decoding order */

2025-12-04T17:15:13Z

Memory decoding order

← Older revision		Revision as of 18:15, 4 December 2025
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	Additionally, there's 16KB + 8KB KB which exist in two instances: as an "internal bram" and as an "external sram":		Additionally, there's 16KB + 8KB KB which exist in two instances: as an "internal bram" and as an "external sram":

	Accesses to bank 5 or bank 7 always go to internal bram with the following three exceptions:		Accesses to (the RAM of 16KB) "bank 5" or (the first 8KB RAM of the RAM of 16KB) "bank 7" always go to internal bram with the following three exceptions:

	1 Layer 2 itself has a direct connection to external sram so while (the core is) reading bytes to generate video, all bytes read come from external sram. It has no connection to internal bram so its bank 5 or bank 7 accesses are from external sram and not internal bram.		1 Layer 2 itself has a direct connection to external sram so while (the core is) reading bytes to generate video, all bytes read come from external sram. It has no connection to internal bram so its "bank 5" or "bank 7" accesses are from external sram and not internal bram.

	2 Layer 2 mapping is a mapping to external sram only. So bank 5 or bank 7 will not come from internal bram but from external sram which is how the cpu can uncover that otherwise hidden memory in external sram.		2 Layer 2 mapping is a mapping to external sram only. So "bank 5" or "bank 7" will not come from internal bram but from external sram which is how the cpu can uncover that otherwise hidden memory in external sram.

	3 The config mapping is also an external sram mapping.		3 The config mapping is also an external sram mapping.

Johnnyo: /* Memory decoding order */

2025-12-04T17:08:12Z

Memory decoding order

← Older revision		Revision as of 18:08, 4 December 2025
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	Finally the remaining top 16k, the 48k-64k area is mapped only by MMU.		Finally the remaining top 16k, the 48k-64k area is mapped only by MMU.

			Additionally, there's 16KB + 8KB KB which exist in two instances: as an "internal bram" and as an "external sram":

			Accesses to bank 5 or bank 7 always go to internal bram with the following three exceptions:

			1 Layer 2 itself has a direct connection to external sram so while (the core is) reading bytes to generate video, all bytes read come from external sram. It has no connection to internal bram so its bank 5 or bank 7 accesses are from external sram and not internal bram.

			2 Layer 2 mapping is a mapping to external sram only. So bank 5 or bank 7 will not come from internal bram but from external sram which is how the cpu can uncover that otherwise hidden memory in external sram.

			3 The config mapping is also an external sram mapping.

	== Paging techniques ==		== Paging techniques ==

Johnnyo: /* Memory decoding order */

2025-12-04T15:51:27Z

Memory decoding order

← Older revision		Revision as of 16:51, 4 December 2025
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	=== Memory decoding order ===		=== Memory decoding order ===

	(check also current [https://gitlab.com/SpectrumNext/ZX_Spectrum_Next_FPGA/-/blob/master/cores/zxnext/src/zxnext.vhd#~~L2870~~ VHDL source])		(check also current [https://gitlab.com/SpectrumNext/ZX_Spectrum_Next_FPGA/-/blob/master/cores/zxnext/src/zxnext.vhd#L2918 VHDL source])

	The 0-16k area could be remapped by several different mechanics, the priority order of these (from highest priority to lowest):		The 0-16k area could be remapped by several different mechanics, the priority order of these (from highest priority to lowest):