Layer 2 - Revision history

Varmfskii: size of hidden memory

2020-11-19T20:03:15Z

size of hidden memory

← Older revision		Revision as of 21:03, 19 November 2020
Line 30:		Line 30:
	With both bits 0 and 2 set you are creating alternative read+write mapping of RAM (technically identical to mapping done by MM0+MMU1 registers).		With both bits 0 and 2 set you are creating alternative read+write mapping of RAM (technically identical to mapping done by MM0+MMU1 registers).

	Bank 5 and first half of Bank 7, when being accessed by regular means (MMU paging, default memory mapping, DMA), are overshadowed by fast BRAM memory inside the FPGA chip, which is then used to generate ULA screen and [[Tilemap]] graphics (aka "Layer 3") - not using the SRAM memory chip in that particular area. This Layer 2 (mapping and visible data) is the only exception, circumventing this mechanism and accessing the Bank 5 and Bank 7 in the main memory SRAM chip (giving you extra 8+~~4kiB~~ of "secret" memory and further headache to emulators' authors). If you are not sure what this means, just avoid using bank 5 and 7 for Layer 2, use values greater/equal to 8 (and avoid also Bank 8, unless you want to destroy NextBASIC warm-restart/soft-reset variables).		Bank 5 and first half of Bank 7, when being accessed by regular means (MMU paging, default memory mapping, DMA), are overshadowed by fast BRAM memory inside the FPGA chip, which is then used to generate ULA screen and [[Tilemap]] graphics (aka "Layer 3") - not using the SRAM memory chip in that particular area. This Layer 2 (mapping and visible data) is the only exception, circumventing this mechanism and accessing the Bank 5 and Bank 7 in the main memory SRAM chip (giving you extra 16+8kiB of "secret" memory and further headache to emulators' authors). If you are not sure what this means, just avoid using bank 5 and 7 for Layer 2, use values greater/equal to 8 (and avoid also Bank 8, unless you want to destroy NextBASIC warm-restart/soft-reset variables).

	Bits 6 and 7 contain the number which third of Layer 2 should be mapped (0..2), or (new feature of core 3.0) when value 3 is set, whole 48kiB of Layer 2 is mapped into area $0000-$bfff (make sure your code, stack and interrupts will cope well with such new mapping).		Bits 6 and 7 contain the number which third of Layer 2 should be mapped (0..2), or (new feature of core 3.0) when value 3 is set, whole 48kiB of Layer 2 is mapped into area $0000-$bfff (make sure your code, stack and interrupts will cope well with such new mapping).

Ped7g: refresh with core 3.1.5 stuff

2020-11-19T18:09:57Z

refresh with core 3.1.5 stuff

← Older revision		Revision as of 19:09, 19 November 2020
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	Layer 2 provides an additional screen layer at ~~256192~~ 256 colours, ~~320240~~ 256 colours or ~~640 * 512~~ 16 colours in which every pixel is individually coloured. Layer 2 may appear in place of, behind, or above the ULA-generated ~~screen~~ / Tilemap. ~~Information for selecting the resolution and banks can be found on NextReg $70 https://wiki.specnext.dev/Layer_2_Control_Register~~		Layer 2 provides an additional screen layer at 256x192 256 colours, 320x256 256 colours or 640x256 16 colours in which every pixel is individually coloured. Layer 2 may appear in place of, behind, or above the ULA-generated/Tilemap layer.

	~~Since core~~ 3.0 the visible Layer 2 ~~will not cause~~ the ~~slow down of CPU~~, ~~even in 14MHz~~ and ~~28MHz modes~~, ~~the machine will operate at same speed~~ as ~~when~~ Layer 2 ~~is invisible~~.		The Layer 2 screen occupies 48kiB or 80kiB, which is stored in 3 (or 5) consecutive [[Memory map\|banks]]. By NextZXOS/NextBASIC default, banks 9-11 are used for the visible and "shadow" Layer 2 screen (the HW after power-on defaults to 8-10 for displayed and 11-13 for shadow screen, but that gets modified by NextZXOS booting up). These can be set using {{NextRegNo\|$12}} and {{NextRegNo\|$13}} (avoid banks 5, 7 and 8 to be used as Layer 2 screen, unless you are familiar with SRAM and BRAM of the board and how the ULA screen memory has special treatment in Next's FPGA).

	~~'''~~This ~~page~~ is ~~updated core2.0 info with core~~ 3.~~0 changes, but may still lack some detail or contain some inaccuracy~~.~~'''~~		Each pixel of Layer 2 is assigned 1 byte of video memory (in 8bpp modes). This means Layer 2 consumes a total of 48kiB (256x192) or 80kiB (320x256). Since the Spectrum banks are 16kiB, Layer 2 256x192 mode is divided horizontally into 3 banks of 64 lines each, each of which is exactly 16kiB. The mode 320x256 (and 640x256) is divided vertically into 5 banks of 64 (128) columns each.

	~~The~~ Layer 2 ~~screen occupies 48kiB, which~~ is ~~stored in 3 consecutive [[Memory map\|banks]]. By default, banks 8-10 are used for the visible Layer 2 screen and banks 11-13 for the shadow Layer 2 screen. These can be set using~~ {{~~NextRegNo~~\|$12}} and {{NextRegNo\|$13}} ~~(avoid banks 5 and 7 to be used as Layer 2 screen~~, ~~unless you are familiar with SRAM and BRAM of the board and how~~ the ~~ULA screen memory has special treatment in Next's FPGA).~~		Layer 2 is controlled via {{PortNo\|$123B}} and {{NextRegNo\|$70}}, the port is bit mapped as follows:

	Each pixel of Layer 2 is assigned 1 byte of video memory. This means Layer 2 consumes a total of 48kiB. Since the Spectrum banks are 16kiB, Layer 2 is divided horizontally into 3 banks of 64 lines each, each of which is exactly 16kiB.

	~~Layer 2 is controlled via {{PortNo\|$123B}}, which~~ is bit mapped as follows:

	{\| class="wikitable"		{\| class="wikitable"
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	With both bits 0 and 2 set you are creating alternative read+write mapping of RAM (technically identical to mapping done by MM0+MMU1 registers).		With both bits 0 and 2 set you are creating alternative read+write mapping of RAM (technically identical to mapping done by MM0+MMU1 registers).

	Bank 5 and first half of Bank 7, when being accessed by regular means (MMU paging, default memory mapping, DMA), are overshadowed by fast BRAM memory inside the FPGA chip, which is then used to generate ULA screen and [[Tilemap]] graphics (aka "Layer 3") - not using the SRAM memory chip in that particular area. This Layer 2 (mapping and visible data) is the only exception, circumventing this mechanism and accessing the Bank 5 and Bank 7 in the main memory SRAM chip (giving you extra 8+4kiB of "secret" memory and further headache to emulators' authors). If you are not sure what this means, just avoid using bank 5 and 7 for Layer 2, use values greater/equal to 8.		Bank 5 and first half of Bank 7, when being accessed by regular means (MMU paging, default memory mapping, DMA), are overshadowed by fast BRAM memory inside the FPGA chip, which is then used to generate ULA screen and [[Tilemap]] graphics (aka "Layer 3") - not using the SRAM memory chip in that particular area. This Layer 2 (mapping and visible data) is the only exception, circumventing this mechanism and accessing the Bank 5 and Bank 7 in the main memory SRAM chip (giving you extra 8+4kiB of "secret" memory and further headache to emulators' authors). If you are not sure what this means, just avoid using bank 5 and 7 for Layer 2, use values greater/equal to 8 (and avoid also Bank 8, unless you want to destroy NextBASIC warm-restart/soft-reset variables).

	Bits 6 and 7 contain the number which third of Layer 2 should be mapped (0..2), or (new feature of core 3.0) when value 3 is set, whole 48kiB of Layer 2 is mapped into area $0000-$bfff (make sure your code, stack and interrupts will cope well with such new mapping).		Bits 6 and 7 contain the number which third of Layer 2 should be mapped (0..2), or (new feature of core 3.0) when value 3 is set, whole 48kiB of Layer 2 is mapped into area $0000-$bfff (make sure your code, stack and interrupts will cope well with such new mapping).

			There is one more new functionality in latest 3.x cores, allowing to set bank-offset variable from 0 to 7. This offset is further applied to the bank selected for write/read (by writing value 0..7 to the port with bit4 set (so it's value 16..23). If you did set for example 16kiB write mapping of first bank, the first bank is 9, and use value 21 for bank-offset setup (+5 offset), the bank mapped into $0000..$3FFF address area will be 14 (9+5). This way you can map full 80kiB of pixel data into the bottom 16kiB window (or bottom 48kiB window), using different offsets.

			Use {{NextRegNo\|$70}} to select particular Layer2 mode, and to modify palette offset (added to top four bits of each pixel). Don't forget to set up Layer 2 clip window correctly for each mode ({{NextRegNo\|$18}}).

	You can still use also the regular [[Memory map\|banking]] ports to switch in one of the Layer 2 banks in slot for at $C000 (or use the ZX Next MMU registers to map that RAM in other regions). This will allow you to read and write the memory as usual. The ability to write to Layer 2 via writes into slot 1 is provided for convenience and to allow graphics data to be easily copied from extended RAM banks.		You can still use also the regular [[Memory map\|banking]] ports to switch in one of the Layer 2 banks in slot for at $C000 (or use the ZX Next MMU registers to map that RAM in other regions). This will allow you to read and write the memory as usual. The ability to write to Layer 2 via writes into slot 1 is provided for convenience and to allow graphics data to be easily copied from extended RAM banks.

	Pixels are drawn to Layer 2 by writing to the appropriate area of RAM. Layer 2 pixels are in English reading order with no ULA-style interlacing. Since there are 256 pixels per line, and when using access via slot 1 the memory port starts at $0000, the upper byte of the address exactly equals the Y coordinate (within the selected third of the screen) and the lower byte exactly equals the X coordinate.		Pixels are drawn to Layer 2 by writing to the appropriate area of RAM. Layer 2 pixels in 256x192 mode are in English reading order with no ULA-style interlacing. Since there are 256 pixels per line, and when using access via slot 1 the memory port starts at $0000, the upper byte of the address exactly equals the Y coordinate (within the selected third of the screen) and the lower byte exactly equals the X coordinate.

			In mode 320x256 (8bpp) the pixels are stored in memory going from top to bottom and left to right (second byte is first pixel on second line, 256th byte is second pixel on first line). Since there are 256 pixels per column, the upper byte of address could represent the X coordinate (only specific range of them, as whole 0..319 range does not fit into 8 bits), and the lower byte of address is Y coordinate. The total pixel memory is 80kiB (five 16kiB banks), and could be mapped into memory either by MMU or by bank-offset feature of {{PortNo\|$123B}}.

			In mode 640x256 (4bpp) the pixels are stored identically to 320x256 mode, but every byte contains two pixels. The top nibble (top four bits) form "left" pixel, and the bottom nibble form "right" pixel, so first 256 bytes will display as two columns on screen, not one.

	Note that you will need to manually clear the Layer 2 screen before drawing on it, as it may contain random data when the machine starts up.		Note that you will need to manually clear the Layer 2 screen before drawing on it, as it may contain random data when the machine starts up.

	System registers {{NextRegNo\|$16}} and {{NextRegNo\|$17}} apply a pixel shift to all content in Layer		System registers {{NextRegNo\|$16}}, {{NextRegNo\|$71}} and {{NextRegNo\|$17}} apply a pixel shift to all content in Layer
	2, allowing scrolling effects to be created.		2, allowing scrolling effects to be created.

	Since core 3.0 the visibility of Layer 2 is not affected by usage of ZX128 ULA-shadow (Bank 7) screen.		Since core 3.0 the visibility of Layer 2 is not affected by usage of ZX128 ULA-shadow (Bank 7) screen.

			Obsolete info for core 2.x (limitation was lifted in core 3.0): <del>the visible Layer 2 will cause the slow down of CPU to 7MHz.</del>

	To use double-buffered scheme for Layer 2, think about {{NextRegNo\|$12}} being display related (i.e. has to be changed to display new Layer 2, when the new image is already prepared) (or it may be modified also during frame to compose final image from various memory areas), while {{NextRegNo\|$13}} is related only to write-over-ROM paging functionality ({{PortNo\|$123B}}).		To use double-buffered scheme for Layer 2, think about {{NextRegNo\|$12}} being display related (i.e. has to be changed to display new Layer 2, when the new image is already prepared) (or it may be modified also during frame to compose final image from various memory areas), while {{NextRegNo\|$13}} is related only to write-over-ROM paging functionality ({{PortNo\|$123B}}).

Em00k: added extra resolutions

2020-11-18T19:35:34Z

added extra resolutions

← Older revision		Revision as of 20:35, 18 November 2020
Line 1:		Line 1:
	Layer 2 is an additional ~~graphics feature on the Next. It provides a 256-color~~ screen at ~~the full 256x192 resolution~~, in which every pixel is individually ~~colored~~. Layer 2 may appear in place of, behind, or above the ULA-generated screen.		Layer 2 provides an additional screen layer at 256192 256 colours, 320240 256 colours or 640 * 512 16 colours in which every pixel is individually coloured. Layer 2 may appear in place of, behind, or above the ULA-generated screen / Tilemap. Information for selecting the resolution and banks can be found on NextReg $70 https://wiki.specnext.dev/Layer_2_Control_Register

	Since core 3.0 the visible Layer 2 will not cause the slow down of CPU, even in 14MHz and 28MHz modes, the machine will operate at same speed as when Layer 2 is invisible.		Since core 3.0 the visible Layer 2 will not cause the slow down of CPU, even in 14MHz and 28MHz modes, the machine will operate at same speed as when Layer 2 is invisible.

Ped7g: core 3.0 changes/refresh

2019-11-27T16:59:00Z

core 3.0 changes/refresh

← Older revision		Revision as of 17:59, 27 November 2019
Line 23:		Line 23:
	\|-		\|-
	\| 1 \|\| Layer 2 visible - {{NextRegNo\|$12}}		\| 1 \|\| Layer 2 visible - {{NextRegNo\|$12}}
			Since core 3.0 this bit has mirror in {{NextRegNo\|$69}}
	\|-		\|-
	\| 0 \|\| Enable Layer 2 write-only paging		\| 0 \|\| Enable Layer 2 write-only paging

Ped7g: core 3.0 changes/refresh

2019-11-27T16:35:08Z

core 3.0 changes/refresh

← Older revision		Revision as of 17:35, 27 November 2019
Line 33:		Line 33:
	With both bits 0 and 2 set you are creating alternative read+write mapping of RAM (technically identical to mapping done by MM0+MMU1 registers).		With both bits 0 and 2 set you are creating alternative read+write mapping of RAM (technically identical to mapping done by MM0+MMU1 registers).

	Bank 5 and first half of Bank 7, when being accessed by regular means (MMU paging ~~and~~ default mapping), are overshadowed by fast BRAM memory inside the FPGA chip, which is then used to generate ULA screen and ~~tilemap~~ graphics (aka "Layer 3") - not using the SRAM memory chip in that particular area. This Layer 2 (mapping and visible data) is the only exception, circumventing this mechanism and accessing the Bank 5 and Bank 7 in the main memory SRAM chip (giving you extra 8+4kiB of "secret" memory and further headache to emulators' authors). If you are not sure what this means, just avoid using bank 5 and 7 for Layer 2, use values greater/equal to 8.		Bank 5 and first half of Bank 7, when being accessed by regular means (MMU paging, default memory mapping, DMA), are overshadowed by fast BRAM memory inside the FPGA chip, which is then used to generate ULA screen and [[Tilemap]] graphics (aka "Layer 3") - not using the SRAM memory chip in that particular area. This Layer 2 (mapping and visible data) is the only exception, circumventing this mechanism and accessing the Bank 5 and Bank 7 in the main memory SRAM chip (giving you extra 8+4kiB of "secret" memory and further headache to emulators' authors). If you are not sure what this means, just avoid using bank 5 and 7 for Layer 2, use values greater/equal to 8.

	Bits 6 and 7 contain the number which third of Layer 2 should be mapped (0..2), or (new feature of core 3.0) when value 3 is set, whole 48kiB of Layer 2 is mapped into area $0000-$bfff (make sure your code, stack and interrupts will cope well with such new mapping).		Bits 6 and 7 contain the number which third of Layer 2 should be mapped (0..2), or (new feature of core 3.0) when value 3 is set, whole 48kiB of Layer 2 is mapped into area $0000-$bfff (make sure your code, stack and interrupts will cope well with such new mapping).

Ped7g: core 3.0 changes/refresh

2019-11-27T16:29:24Z

core 3.0 changes/refresh

← Older revision		Revision as of 17:29, 27 November 2019
Line 1:		Line 1:
	Layer 2 is an additional graphics feature on the Next. It provides a 256-color screen at the full 256x192 resolution, in which every pixel is individually colored. Layer 2 may appear in place of, behind, or above the ULA-generated screen.		Layer 2 is an additional graphics feature on the Next. It provides a 256-color screen at the full 256x192 resolution, in which every pixel is individually colored. Layer 2 may appear in place of, behind, or above the ULA-generated screen.

	~~At this moment~~ the ~~enabled~~ Layer 2 ~~prevents turbo mode 14MHz to be stable, the ZX Next~~ will ~~thus drop the speed to 7MHz automatically when video-out signal for~~ the ~~central 256x192 pixel area~~ of ~~screen is generated. For remaining areas of screen (border~~, and ~~H/V-blanks)~~ the ~~CPU~~ will operate at ~~desired 14MHz~~ speed ~~even with~~ Layer 2 ~~enabled~~.		Since core 3.0 the visible Layer 2 will not cause the slow down of CPU, even in 14MHz and 28MHz modes, the machine will operate at same speed as when Layer 2 is invisible.

	'''~~Documentation on Layer 2~~ is ~~extremely sparse at the moment and could be subject to change~~.''' ~~Information below has been taken from emulator documentation.~~		'''This page is updated core2.0 info with core 3.0 changes, but may still lack some detail or contain some inaccuracy.'''

	The Layer 2 screen occupies ~~48k~~, which is stored in 3 consecutive [[Memory map\|banks]]. By default, banks 8-10 are used for the ~~main~~ Layer 2 screen and banks 11-13 for the shadow Layer 2 screen. These can be ~~changed~~ using {{NextRegNo\|$12}} and {{NextRegNo\|$13}}.		The Layer 2 screen occupies 48kiB, which is stored in 3 consecutive [[Memory map\|banks]]. By default, banks 8-10 are used for the visible Layer 2 screen and banks 11-13 for the shadow Layer 2 screen. These can be set using {{NextRegNo\|$12}} and {{NextRegNo\|$13}} (avoid banks 5 and 7 to be used as Layer 2 screen, unless you are familiar with SRAM and BRAM of the board and how the ULA screen memory has special treatment in Next's FPGA).

	Each pixel of Layer 2 is assigned 1 byte of video memory. This means Layer 2 consumes a total of ~~48k~~. Since the Spectrum banks are ~~16k~~, Layer 2 is divided horizontally into 3 banks of 64 lines each, each of which is exactly ~~16k~~.		Each pixel of Layer 2 is assigned 1 byte of video memory. This means Layer 2 consumes a total of 48kiB. Since the Spectrum banks are 16kiB, Layer 2 is divided horizontally into 3 banks of 64 lines each, each of which is exactly 16kiB.

	Layer 2 is controlled via {{PortNo\|$123B}}, which is bit mapped as follows:		Layer 2 is controlled via {{PortNo\|$123B}}, which is bit mapped as follows:
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	! Bit !! Description		! Bit !! Description
	\|-		\|-
	\| 6-7 \|\| Video RAM bank select		\| 7-6 \|\| Video RAM bank select (write/read paging)
	\|-		\|-
	\| 3 \|\| ~~Shadow Layer 2 RAM select~~		\| 5-4 \|\| Reserved, write 0
	\|-		\|-
	\| 1 \|\| Layer 2 ~~visible~~		\| 3 \|\| Use Shadow Layer 2 for paging - {{NextRegNo\|$13}}
	\|-		\|-
	\| 0 \|\| Enable Layer 2 write paging		\| 2 \|\| Enable Layer 2 read-only paging
			\|-
			\| 1 \|\| Layer 2 visible - {{NextRegNo\|$12}}
			\|-
			\| 0 \|\| Enable Layer 2 write-only paging
	\|}		\|}

	When bit 0 of $123B is set to 1, the appropriate area of Layer 2 video memory (as set by bits 6-7) is accessed by '''writes''' into slot 1, ie memory area $0000-$3fff (see [[Memory map]]). This prevents any conflict since this area would normally be ROM and thus useless to write to. However, you '''cannot READ the contents of Layer 2 via this mapping!''' Reading addresses in this range will read the values from the ROM page (or RAM bank if in AllRam mode) that would be mapped there normally if Layer 2 ~~were~~ disabled.		When bit 0 of $123B is set to 1, the appropriate area of Layer 2 video memory (as set by bits 6-7) is accessed by '''writes''' into slot 1, ie memory area $0000-$3fff (see [[Memory map]]). This prevents any conflict since this area would normally be ROM and thus useless to write to. However, you '''cannot READ the contents of Layer 2 via this mapping!''' Reading addresses in this range will read the values from the ROM page (or RAM bank if in AllRam mode) that would be mapped there normally if Layer 2 paging was disabled.

			When bit 2 of $123B is set to 1 (new feature of core 3.0), the same area $0000-$3fff is remapped for read, allowing read access into Layer 2 bank selected by bits 3,6 and 7 (while write will still go into the regular ROM/RAM page).

			With both bits 0 and 2 set you are creating alternative read+write mapping of RAM (technically identical to mapping done by MM0+MMU1 registers).

			Bank 5 and first half of Bank 7, when being accessed by regular means (MMU paging and default mapping), are overshadowed by fast BRAM memory inside the FPGA chip, which is then used to generate ULA screen and tilemap graphics (aka "Layer 3") - not using the SRAM memory chip in that particular area. This Layer 2 (mapping and visible data) is the only exception, circumventing this mechanism and accessing the Bank 5 and Bank 7 in the main memory SRAM chip (giving you extra 8+4kiB of "secret" memory and further headache to emulators' authors). If you are not sure what this means, just avoid using bank 5 and 7 for Layer 2, use values greater/equal to 8.

			Bits 6 and 7 contain the number which third of Layer 2 should be mapped (0..2), or (new feature of core 3.0) when value 3 is set, whole 48kiB of Layer 2 is mapped into area $0000-$bfff (make sure your code, stack and interrupts will cope well with such new mapping).

	~~If you need to ''read'' from Layer 2 you~~ can use the regular [[Memory map\|banking]] ports to switch in one of the Layer 2 banks in slot for at $C000. This will allow you to read and write the memory as usual. The ability to write to Layer 2 via writes into slot 1 is provided for convenience and to allow graphics data to be easily copied from extended RAM banks.		You can still use also the regular [[Memory map\|banking]] ports to switch in one of the Layer 2 banks in slot for at $C000 (or use the ZX Next MMU registers to map that RAM in other regions). This will allow you to read and write the memory as usual. The ability to write to Layer 2 via writes into slot 1 is provided for convenience and to allow graphics data to be easily copied from extended RAM banks.

	Pixels are drawn to Layer 2 by writing to the appropriate area of RAM. Layer 2 pixels are in English reading order with no ULA-style interlacing. Since there are 256 pixels per line, and when using access via slot 1 the memory port starts at $0000, the upper byte of the address exactly equals the Y coordinate (within the selected third of the screen) and the lower byte exactly equals the X coordinate.		Pixels are drawn to Layer 2 by writing to the appropriate area of RAM. Layer 2 pixels are in English reading order with no ULA-style interlacing. Since there are 256 pixels per line, and when using access via slot 1 the memory port starts at $0000, the upper byte of the address exactly equals the Y coordinate (within the selected third of the screen) and the lower byte exactly equals the X coordinate.
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	Note that you will need to manually clear the Layer 2 screen before drawing on it, as it may contain random data when the machine starts up.		Note that you will need to manually clear the Layer 2 screen before drawing on it, as it may contain random data when the machine starts up.

	System registers {{NextRegNo\|$16}} and {{NextRegNo\|$17}} apply a pixel shift to all content in Layer 2, allowing scrolling effects to be created.		System registers {{NextRegNo\|$16}} and {{NextRegNo\|$17}} apply a pixel shift to all content in Layer
			2, allowing scrolling effects to be created.

	~~When ZX Spectrum 128k {{PortNo\|$7FFD}} is used to switch display to ULA "shadow" variant,~~ the Layer 2 is ~~automatically disabled, due to~~ ULA ~~screen data being read from other memory bank. For double~~-~~buffered ULA~~ screen ~~together with Layer 2 functionality, use the {{PortNo\|$xxFF}} functionality~~.		Since core 3.0 the visibility of Layer 2 is not affected by usage of ZX128 ULA-shadow (Bank 7) screen.

	To use double-buffered scheme for Layer 2, think about {{NextRegNo\|$12}} being display related (i.e. has to be changed to display new Layer 2, when the new image is already prepared) (or it may be modified also during frame to compose final image from various memory areas), while {{NextRegNo\|$13}} is related only to write-over-ROM functionality ({{PortNo\|$123B}}).		To use double-buffered scheme for Layer 2, think about {{NextRegNo\|$12}} being display related (i.e. has to be changed to display new Layer 2, when the new image is already prepared) (or it may be modified also during frame to compose final image from various memory areas), while {{NextRegNo\|$13}} is related only to write-over-ROM paging functionality ({{PortNo\|$123B}}).

Cthutu: Removed previous edit.

2019-06-19T22:04:55Z

Removed previous edit.

← Older revision		Revision as of 23:04, 19 June 2019
Line 17:		Line 17:
	\|-		\|-
	\| 3 \|\| Shadow Layer 2 RAM select		\| 3 \|\| Shadow Layer 2 RAM select
	\|-
	~~\| 2 \|\| Enable Layer 2 read when Layer 2 write paging is enabled~~
	\|-		\|-
	\| 1 \|\| Layer 2 visible		\| 1 \|\| Layer 2 visible
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	When bit 0 of $123B is set to 1, the appropriate area of Layer 2 video memory (as set by bits 6-7) is accessed by '''writes''' into slot 1, ie memory area $0000-$3fff (see [[Memory map]]). This prevents any conflict since this area would normally be ROM and thus useless to write to. However, you '''cannot READ the contents of Layer 2 via this mapping!''' Reading addresses in this range will read the values from the ROM page (or RAM bank if in AllRam mode) that would be mapped there normally if Layer 2 were disabled.		When bit 0 of $123B is set to 1, the appropriate area of Layer 2 video memory (as set by bits 6-7) is accessed by '''writes''' into slot 1, ie memory area $0000-$3fff (see [[Memory map]]). This prevents any conflict since this area would normally be ROM and thus useless to write to. However, you '''cannot READ the contents of Layer 2 via this mapping!''' Reading addresses in this range will read the values from the ROM page (or RAM bank if in AllRam mode) that would be mapped there normally if Layer 2 were disabled.

	If you need to ''read'' from Layer 2 ~~you can either set bit 2 of $123B, or~~ you can use the regular [[Memory map\|banking]] ports to switch in one of the Layer 2 banks in slot for at $C000. This will allow you to read and write the memory as usual. The ability to write to Layer 2 via writes into slot 1 is provided for convenience and to allow graphics data to be easily copied from extended RAM banks.		If you need to ''read'' from Layer 2 you can use the regular [[Memory map\|banking]] ports to switch in one of the Layer 2 banks in slot for at $C000. This will allow you to read and write the memory as usual. The ability to write to Layer 2 via writes into slot 1 is provided for convenience and to allow graphics data to be easily copied from extended RAM banks.

	Pixels are drawn to Layer 2 by writing to the appropriate area of RAM. Layer 2 pixels are in English reading order with no ULA-style interlacing. Since there are 256 pixels per line, and when using access via slot 1 the memory port starts at $0000, the upper byte of the address exactly equals the Y coordinate (within the selected third of the screen) and the lower byte exactly equals the X coordinate.		Pixels are drawn to Layer 2 by writing to the appropriate area of RAM. Layer 2 pixels are in English reading order with no ULA-style interlacing. Since there are 256 pixels per line, and when using access via slot 1 the memory port starts at $0000, the upper byte of the address exactly equals the Y coordinate (within the selected third of the screen) and the lower byte exactly equals the X coordinate.

Cthutu: Documented bit 2.

2019-06-19T20:52:20Z

Documented bit 2.

← Older revision		Revision as of 21:52, 19 June 2019
Line 17:		Line 17:
	\|-		\|-
	\| 3 \|\| Shadow Layer 2 RAM select		\| 3 \|\| Shadow Layer 2 RAM select
			\|-
			\| 2 \|\| Enable Layer 2 read when Layer 2 write paging is enabled
	\|-		\|-
	\| 1 \|\| Layer 2 visible		\| 1 \|\| Layer 2 visible
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	When bit 0 of $123B is set to 1, the appropriate area of Layer 2 video memory (as set by bits 6-7) is accessed by '''writes''' into slot 1, ie memory area $0000-$3fff (see [[Memory map]]). This prevents any conflict since this area would normally be ROM and thus useless to write to. However, you '''cannot READ the contents of Layer 2 via this mapping!''' Reading addresses in this range will read the values from the ROM page (or RAM bank if in AllRam mode) that would be mapped there normally if Layer 2 were disabled.		When bit 0 of $123B is set to 1, the appropriate area of Layer 2 video memory (as set by bits 6-7) is accessed by '''writes''' into slot 1, ie memory area $0000-$3fff (see [[Memory map]]). This prevents any conflict since this area would normally be ROM and thus useless to write to. However, you '''cannot READ the contents of Layer 2 via this mapping!''' Reading addresses in this range will read the values from the ROM page (or RAM bank if in AllRam mode) that would be mapped there normally if Layer 2 were disabled.

	If you need to ''read'' from Layer 2 you ~~will need to~~ use the regular [[Memory map\|banking]] ports to switch in one of the Layer 2 banks in slot for at $C000. This will allow you to read and write the memory as usual. The ability to write to Layer 2 via writes into slot 1 is provided for convenience and to allow graphics data to be easily copied from extended RAM banks.		If you need to ''read'' from Layer 2 you can either set bit 2 of $123B, or you can use the regular [[Memory map\|banking]] ports to switch in one of the Layer 2 banks in slot for at $C000. This will allow you to read and write the memory as usual. The ability to write to Layer 2 via writes into slot 1 is provided for convenience and to allow graphics data to be easily copied from extended RAM banks.

	Pixels are drawn to Layer 2 by writing to the appropriate area of RAM. Layer 2 pixels are in English reading order with no ULA-style interlacing. Since there are 256 pixels per line, and when using access via slot 1 the memory port starts at $0000, the upper byte of the address exactly equals the Y coordinate (within the selected third of the screen) and the lower byte exactly equals the X coordinate.		Pixels are drawn to Layer 2 by writing to the appropriate area of RAM. Layer 2 pixels are in English reading order with no ULA-style interlacing. Since there are 256 pixels per line, and when using access via slot 1 the memory port starts at $0000, the upper byte of the address exactly equals the Y coordinate (within the selected third of the screen) and the lower byte exactly equals the X coordinate.

Julian S at 15:31, 26 April 2019

2019-04-26T15:31:03Z

← Older revision		Revision as of 16:31, 26 April 2019
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	'''Documentation on Layer 2 is extremely sparse at the moment and could be subject to change.''' Information below has been taken from emulator documentation.		'''Documentation on Layer 2 is extremely sparse at the moment and could be subject to change.''' Information below has been taken from emulator documentation.

	The ~~layer~~ 2 screen occupies 48k, which is stored in 3 consecutive [[Memory map\|banks]]. By default, banks 8-10 are used for the main ~~layer~~ 2 screen and banks 11-13 for the shadow ~~layer~~ 2 screen. These can be changed using {{NextRegNo\|$12}} and {{NextRegNo\|$13}}.		The Layer 2 screen occupies 48k, which is stored in 3 consecutive [[Memory map\|banks]]. By default, banks 8-10 are used for the main Layer 2 screen and banks 11-13 for the shadow Layer 2 screen. These can be changed using {{NextRegNo\|$12}} and {{NextRegNo\|$13}}.

	Each pixel of ~~layer~~ 2 is assigned 1 byte of video memory. This means ~~layer~~ 2 consumes a total of 48k. Since the Spectrum banks are 16k, Layer 2 is divided horizontally into 3 banks of 64 lines each, each of which is exactly 16k.		Each pixel of Layer 2 is assigned 1 byte of video memory. This means Layer 2 consumes a total of 48k. Since the Spectrum banks are 16k, Layer 2 is divided horizontally into 3 banks of 64 lines each, each of which is exactly 16k.

	Layer 2 is controlled via {{PortNo\|$123B}}, which is bit mapped as follows:		Layer 2 is controlled via {{PortNo\|$123B}}, which is bit mapped as follows:
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	\|}		\|}

	When bit 0 of $123B is set to 1, the appropriate area of Layer 2 video memory (as set by bits 6-7) is accessed by '''writes''' into slot 1, ie memory area $0000-$3fff (see [[Memory map]]). This prevents any conflict since this area would normally be ROM and thus useless to write to. However, you '''cannot READ the contents of ~~layer~~ 2 via this mapping!''' Reading addresses in this range will read the values from the ROM page (or RAM bank if in AllRam mode) that would be mapped there normally if Layer 2 were disabled.		When bit 0 of $123B is set to 1, the appropriate area of Layer 2 video memory (as set by bits 6-7) is accessed by '''writes''' into slot 1, ie memory area $0000-$3fff (see [[Memory map]]). This prevents any conflict since this area would normally be ROM and thus useless to write to. However, you '''cannot READ the contents of Layer 2 via this mapping!''' Reading addresses in this range will read the values from the ROM page (or RAM bank if in AllRam mode) that would be mapped there normally if Layer 2 were disabled.

	If you need to ''read'' from Layer 2 you will need to use the regular [[Memory map\|banking]] ports to switch in one of the ~~layer~~ 2 banks in slot for at $C000. This will allow you to read and write the memory as usual. The ability to write to Layer 2 via writes into ~~Slot~~ 1 is provided for convenience and to allow graphics data to be easily copied from extended RAM banks.		If you need to ''read'' from Layer 2 you will need to use the regular [[Memory map\|banking]] ports to switch in one of the Layer 2 banks in slot for at $C000. This will allow you to read and write the memory as usual. The ability to write to Layer 2 via writes into slot 1 is provided for convenience and to allow graphics data to be easily copied from extended RAM banks.

	Pixels are drawn to ~~layer~~ 2 by writing to the appropriate area of RAM. Layer 2 pixels are in English reading order with no ULA-style interlacing. Since there are 256 pixels per line, and when using access via slot 1 the memory port starts at $0000, the upper byte of the address exactly equals the Y coordinate (within the selected third of the screen) and the lower byte exactly equals the X coordinate.		Pixels are drawn to Layer 2 by writing to the appropriate area of RAM. Layer 2 pixels are in English reading order with no ULA-style interlacing. Since there are 256 pixels per line, and when using access via slot 1 the memory port starts at $0000, the upper byte of the address exactly equals the Y coordinate (within the selected third of the screen) and the lower byte exactly equals the X coordinate.

	Note that you will need to manually clear the ~~layer~~ 2 screen before drawing on it, as it may contain random data when the machine starts up.		Note that you will need to manually clear the Layer 2 screen before drawing on it, as it may contain random data when the machine starts up.

	System registers {{NextRegNo\|$16}} and {{NextRegNo\|$17}} apply a pixel shift to all content in ~~layer~~ 2, allowing scrolling effects to be created.		System registers {{NextRegNo\|$16}} and {{NextRegNo\|$17}} apply a pixel shift to all content in Layer 2, allowing scrolling effects to be created.

	When ZX Spectrum 128k {{PortNo\|$7FFD}} is used to switch display to ULA "shadow" variant, the Layer 2 is automatically disabled, due to ULA screen data being read from other memory bank. For double-buffered ULA screen together with Layer 2 functionality, use the {{PortNo\|$xxFF}} functionality.		When ZX Spectrum 128k {{PortNo\|$7FFD}} is used to switch display to ULA "shadow" variant, the Layer 2 is automatically disabled, due to ULA screen data being read from other memory bank. For double-buffered ULA screen together with Layer 2 functionality, use the {{PortNo\|$xxFF}} functionality.

	To use double-buffered scheme for Layer 2, think about {{NextRegNo\|$12}} being display related (i.e. has to be changed to display new Layer 2, when the new image is already prepared) (or it may be modified also during frame to compose final image from various memory areas), while {{NextRegNo\|$13}} is related only to write-over-ROM functionality ({{PortNo\|$123B}}).		To use double-buffered scheme for Layer 2, think about {{NextRegNo\|$12}} being display related (i.e. has to be changed to display new Layer 2, when the new image is already prepared) (or it may be modified also during frame to compose final image from various memory areas), while {{NextRegNo\|$13}} is related only to write-over-ROM functionality ({{PortNo\|$123B}}).

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2019-04-14T10:00:16Z

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