Internal Port Decoding b8-15 Register - Revision history

Ped7g: core 3.1.3 changes/refresh

2020-04-13T18:44:06Z

core 3.1.3 changes/refresh

← Older revision		Revision as of 19:44, 13 April 2020
Line 25:		Line 25:
	\|}		\|}

	All bits are set to 1 upon soft reset.		since core3.1.1: all bits are set to 1 when: soft reset and bit 31 is set OR hard reset and bit 31 is clear (otherwise content is kept intact). <del>All bits are set to 1 upon soft reset.</del>

	The internal port decoding enables always apply.		The internal port decoding enables always apply.

Ped7g: core 3.0 changes/refresh

2019-11-12T09:15:57Z

core 3.0 changes/refresh

← Older revision		Revision as of 10:15, 12 November 2019
Line 26:		Line 26:

	All bits are set to 1 upon soft reset.		All bits are set to 1 upon soft reset.

			The internal port decoding enables always apply.

			When the expansion bus is on, the expansion port decoding (Next Registers $86-$89) enables are logically ANDed with the internal enables (Next Registers $82-$85). A zero bit indicates the internal device is disabled.

			If the expansion bus is on, this allows I/O cycles for disabled internal ports to propagate to the expansion bus, otherwise corresponding I/O cycles to the expansion bus are filtered.

	(note: Next registers with number higher than $7F are inaccessible from Copper code)		(note: Next registers with number higher than $7F are inaccessible from Copper code)

Ped7g: core 3.0 changes/refresh

2019-11-12T09:07:44Z

core 3.0 changes/refresh

← Older revision		Revision as of 10:07, 12 November 2019
Line 3:		Line 3:
	\|Readable=Yes		\|Readable=Yes
	\|Writable=Yes		\|Writable=Yes
	\|ShortDesc=Enabling internal ports		\|ShortDesc=Enabling internal ports decoding
	}}		}}
	{\|class="wikitable"		{\|class="wikitable"

Ped7g: core 3.0 changes/refresh

2019-11-12T08:49:26Z

core 3.0 changes/refresh

New page

{{NextRegister
|Number=$83
|Readable=Yes
|Writable=Yes
|ShortDesc=Enabling internal ports
}}
{|class="wikitable"
! Bit !! Description
|-
| 7 || (bit 15) Enabling {{PortNo|$123B}}
|-
| 6 || (bit 14) Enabling {{PortNo|$xx57}}, {{PortNo|$xx5B}} and {{PortNo|$303B}}
|-
| 5 || (bit 13) Enabling {{PortNo|$FADF}}, {{PortNo|$FBDF}} and {{PortNo|$FFDF}}
|-
| 4 || (bit 12) Enabling {{PortNo|$133B}}, {{PortNo|$143B}} and {{PortNo|$153B}} (UART)
|-
| 3 || (bit 11) Enabling {{PortNo|$xxE7}} and {{PortNo|$xxEB}} (SPI)
|-
| 2 || (bit 10) Enabling {{PortNo|$103B}} and {{PortNo|$113B}}
|-
| 1 || (bit 9) Enabling Multiface (two variable ports)
|-
| 0 || (bit 8) Enabling {{PortNo|$xxE3}} (DivMMC control)
|}

All bits are set to 1 upon soft reset.

(note: Next registers with number higher than $7F are inaccessible from Copper code)