Internal Port Decoding b24-31 Register - Revision history

Ped7g: core 3.1.3 changes/refresh

2020-04-13T18:57:28Z

core 3.1.3 changes/refresh

← Older revision		Revision as of 19:57, 13 April 2020
Line 7:		Line 7:
	{\|class="wikitable"		{\|class="wikitable"
	! Bit !! Description		! Bit !! Description

	\|-		\|-
	\| 7-1 \|\| (bit 31-25) Reserved, preserve the current value (or at least use 1)		\| 7 \|\| (bit 31) (since core3.1.1) re-init all bits 0-31 to 1 upon:
			0: hard reset
			<br>1: soft reset
			\|-
			\| 6-2 \|\| (bit 30-26) Reserved, preserve the current value (or at least use 1)

			\|-
			\| 1 \|\| (bit 25) Enabling {{PortNo\|$xx0B}} (since core3.1.2)

	\|-		\|-
	\| 0 \|\| (bit 24) Enabling {{PortNo\|$BF3B}} and {{PortNo\|$FF3B}} (ULA+)		\| 0 \|\| (bit 24) Enabling {{PortNo\|$BF3B}} and {{PortNo\|$FF3B}} (ULA+)
	\|}		\|}

	All bits are set to 1 upon soft reset.		since core3.1.1: all bits are set to 1 when: soft reset and bit 31 is set OR hard reset and bit 31 is clear (otherwise content is kept intact). <del>All bits are set to 1 upon soft reset.</del>

	The internal port decoding enables always apply.		The internal port decoding enables always apply.

Ped7g: core 3.0 changes/refresh

2019-11-12T10:26:49Z

core 3.0 changes/refresh

← Older revision		Revision as of 11:26, 12 November 2019
Line 8:		Line 8:
	! Bit !! Description		! Bit !! Description
	\|-		\|-
	\| 7-1 \|\| (bit 31-25) Reserved, use 1 ~~(? to be confirmed~~)		\| 7-1 \|\| (bit 31-25) Reserved, preserve the current value (or at least use 1)
	\|-		\|-
	\| 0 \|\| (bit 24) Enabling {{PortNo\|$BF3B}} and {{PortNo\|$FF3B}} (ULA+)		\| 0 \|\| (bit 24) Enabling {{PortNo\|$BF3B}} and {{PortNo\|$FF3B}} (ULA+)

Ped7g: core 3.0 changes/refresh

2019-11-12T09:16:49Z

core 3.0 changes/refresh

← Older revision		Revision as of 10:16, 12 November 2019
Line 14:		Line 14:

	All bits are set to 1 upon soft reset.		All bits are set to 1 upon soft reset.

			The internal port decoding enables always apply.

			When the expansion bus is on, the expansion port decoding (Next Registers $86-$89) enables are logically ANDed with the internal enables (Next Registers $82-$85). A zero bit indicates the internal device is disabled.

			If the expansion bus is on, this allows I/O cycles for disabled internal ports to propagate to the expansion bus, otherwise corresponding I/O cycles to the expansion bus are filtered.

	(note: Next registers with number higher than $7F are inaccessible from Copper code)		(note: Next registers with number higher than $7F are inaccessible from Copper code)

Ped7g: core 3.0 changes/refresh

2019-11-12T09:05:40Z

core 3.0 changes/refresh

New page

{{NextRegister
|Number=$85
|Readable=Yes
|Writable=Yes
|ShortDesc=Enabling internal ports decoding
}}
{|class="wikitable"
! Bit !! Description
|-
| 7-1 || (bit 31-25) Reserved, use 1 (? to be confirmed)
|-
| 0 || (bit 24) Enabling {{PortNo|$BF3B}} and {{PortNo|$FF3B}} (ULA+)
|}

All bits are set to 1 upon soft reset.

(note: Next registers with number higher than $7F are inaccessible from Copper code)