Extended Z80 instruction set - Revision history

Johnnyo: /* Z80N instructions opcodes */ removed "2 x code" marks, fixed value in TEST line

2026-01-17T14:03:45Z

Z80N instructions opcodes: removed "2 x code" marks, fixed value in TEST line

Sol HSA: link fixes

2025-10-07T14:39:23Z

link fixes

← Older revision		Revision as of 15:39, 7 October 2025
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	This is a general list of Z80 and Z80N instructions with descriptions. The instructions specific to Z80N have the [[#Z80N_instructions_opcodes\|encodings described first]].		This is a general list of Z80 and Z80N instructions with descriptions. The instructions specific to Z80N have the [[#Z80N_instructions_opcodes\|encodings described first]].

	For a table of summaries without additional descriptions see the [[Z80 Instruction Table]]. There's also ~~a [[Special:RunQuery/OpcodeQuery\|special search for opcodes in the same table]] and~~ an external [https://table.specnext.dev/ Z80N opcode value matrix on specnext.dev].		For a table of summaries without additional descriptions see the [[Z80 Instruction Table]]. There's also an external [https://table.specnext.dev/ Z80N opcode value matrix on specnext.dev].

	=== Z80N instructions opcodes ===		=== Z80N instructions opcodes ===
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	\|<code>NEXTREG n, A </code>\|\|Immediate \|\|Accumulator \|\|E \|\|- \|\|- \|\|- \|\|- \|\|- \|\|- \|\|17 \|\|HwNextReg_n:=A		\|<code>NEXTREG n, A </code>\|\|Immediate \|\|Accumulator \|\|E \|\|- \|\|- \|\|- \|\|- \|\|- \|\|- \|\|17 \|\|HwNextReg_n:=A
	\|}		\|}
	:Next extended opcode. Directly sets the [[Board feature control\|Next Feature Control Registers]] without going through ports ~~{{PortNo\|$243B}}~~ and ~~{{PortNo\|$253B}}~~.		:Next extended opcode. Directly sets the [[Board feature control\|Next Feature Control Registers]] without going through ports [[TBBlue_Register_Select]] and [[TBBlue Register Access]].

	=== A note on some Z80-N specific observations ===		=== A note on some Z80-N specific observations ===

Sol HSA: remove one }}

2025-10-07T12:18:11Z

remove one }}

← Older revision		Revision as of 13:18, 7 October 2025
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	\|-		\|-
	\|<code>PUSH nn </code>\|\|Immediate \|\|- \|\|E \|\|- \|\|- \|\|- \|\|- \|\|- \|\|- \|\|23 \|\|SP-=2; SP*:=nn		\|<code>PUSH nn </code>\|\|Immediate \|\|- \|\|E \|\|- \|\|- \|\|- \|\|- \|\|- \|\|- \|\|23 \|\|SP-=2; SP*:=nn
	}}

	\|}		\|}
	:Pushes the given argument on the stack. This can be any 16-bit register pair except SP. SP is reduced by 2 and then the argument is written to the new location SP points to.		:Pushes the given argument on the stack. This can be any 16-bit register pair except SP. SP is reduced by 2 and then the argument is written to the new location SP points to.

Sol HSA: removed margin:auto

2025-10-07T11:58:52Z

removed margin:auto

Show changes

Sol HSA: rebuilt tables

2025-10-07T11:57:55Z

rebuilt tables

Show changes

Xalior: /* A note on some Z80-N specific observations */

2025-01-27T11:48:36Z

A note on some Z80-N specific observations

← Older revision		Revision as of 12:48, 27 January 2025
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	=== A note on some Z80-N specific observations ===		=== A note on some Z80-N specific observations ===
	2021-09-16: figuring out the hard way, the three Z80N instructions `ADD HL/DE/BC,A` actually do NOT preserve carry flag, but change it to undefined value (verified with core 3.1.5). There's also strong suspicion (but not verified yet), that LDIX/LDDX/LDIRX/LDDRX/LDPIRX do affects flags the same way as LDI/LDIR - to be verified.		2021-09-16: figuring out the hard way, the three Z80N instructions `ADD HL/DE/BC,A` actually do NOT preserve carry flag, but change it to undefined value (verified with core 3.1.5). There's also strong suspicion (but not verified yet), that LDIX/LDDX/LDIRX/LDDRX/LDPIRX do affects flags the same way as LDI/LDIR - to be verified.

			2025-01-25: Testing 3.02.x 1) <code>LDIX</code>, <code>LDDX</code>, <code>LDIRX</code>, <code>LDDRX</code> affect the flags similarly to <code>LDI</code>, <code>LDD</code>, <code>LDIR</code> and <code>LDDR</code>. 2) <code>ADD HL,A</code>, <code>ADD DE,A</code> and <code>ADD BC,A</code> most probably always reset the carry flag.

	=== Errata ===		=== Errata ===

Xalior: Revert to old language, before trying to add back the useful bits.

2025-01-27T11:47:33Z

Revert to old language, before trying to add back the useful bits.

← Older revision		Revision as of 12:47, 27 January 2025
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	=== A note on some Z80-N specific observations ===		=== A note on some Z80-N specific observations ===
			2021-09-16: figuring out the hard way, the three Z80N instructions `ADD HL/DE/BC,A` actually do NOT preserve carry flag, but change it to undefined value (verified with core 3.1.5). There's also strong suspicion (but not verified yet), that LDIX/LDDX/LDIRX/LDDRX/LDPIRX do affects flags the same way as LDI/LDIR - to be verified.
	~~2025~~-01-25: ~~Most of~~ the ~~information on this page about how~~ the Z80N~~-specific~~ instructions ~~exactly affect the flags is a result of users writing here about their experiments. Such experiments currently suggest that~~, ~~at least in the current~~ core: 1) ~~<code>~~LDIX</~~code>, <code>~~LDDX</~~code>, <code>~~LDIRX</~~code>, <code>~~LDDRX</~~code> affect~~ the ~~flags similarly to <code>~~LDI~~</code>, <code>LDD<~~/~~code>, <code>~~LDIR~~</code> and <code>LDDR</code>. 2) <code>ADD HL,A</code>, <code>ADD DE,A</code> and <code>ADD BC,A</code> most probably always reset the carry flag~~.

	=== Errata ===		=== Errata ===

Johnnyo: /* A note on some Z80-N specific observations */ typo

2025-01-25T17:31:01Z

A note on some Z80-N specific observations: typo

← Older revision		Revision as of 18:31, 25 January 2025
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	=== A note on some Z80-N specific observations ===		=== A note on some Z80-N specific observations ===

	2025-01-25: Most of the information on this page about how the Z80N-specific instructions exactly affect the flags is a result of users writing here about their experiments. Such experiments currently suggest that, at least in the current core: 1) <code>LDIX</code>, <code>LDDX</code>, <code>LDIRX</code>, <code>LDDRX</code> affect the flags similarly to <code>LDI</code>, <code>LDD</code>, <code>LDIR</code> and <code>LDDR</code>. 2) <code>ADD HL,A</code>, <code>ADD~~</code>~~ DE,A</code> and <code>ADD BC,A</code> most probably always reset the carry flag.		2025-01-25: Most of the information on this page about how the Z80N-specific instructions exactly affect the flags is a result of users writing here about their experiments. Such experiments currently suggest that, at least in the current core: 1) <code>LDIX</code>, <code>LDDX</code>, <code>LDIRX</code>, <code>LDDRX</code> affect the flags similarly to <code>LDI</code>, <code>LDD</code>, <code>LDIR</code> and <code>LDDR</code>. 2) <code>ADD HL,A</code>, <code>ADD DE,A</code> and <code>ADD BC,A</code> most probably always reset the carry flag.

	=== Errata ===		=== Errata ===

Johnnyo: /* Open Issues */ => A note on some Z80-N specific observations

2025-01-25T17:30:18Z

Open Issues: => A note on some Z80-N specific observations

← Older revision		Revision as of 18:30, 25 January 2025
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	:Next extended opcode. Directly sets the [[Board feature control\|Next Feature Control Registers]] without going through ports {{PortNo\|$243B}} and {{PortNo\|$253B}}.		:Next extended opcode. Directly sets the [[Board feature control\|Next Feature Control Registers]] without going through ports {{PortNo\|$243B}} and {{PortNo\|$253B}}.

	=== ~~Open Issues~~ ===		=== A note on some Z80-N specific observations ===

	~~2021~~-09-16: It is ~~still not confirmed but it seems~~ that LDIX/LDDX/LDIRX/LDDRX/~~LDPIRX could~~ affect flags ~~the same way as~~ LDI/LDIR ~~- (Ped: '''TO DO'''~~). ~~(Note: That behaviour could maybe change in the later cores?)~~		2025-01-25: Most of the information on this page about how the Z80N-specific instructions exactly affect the flags is a result of users writing here about their experiments. Such experiments currently suggest that, at least in the current core: 1) <code>LDIX</code>, <code>LDDX</code>, <code>LDIRX</code>, <code>LDDRX</code> affect the flags similarly to <code>LDI</code>, <code>LDD</code>, <code>LDIR</code> and <code>LDDR</code>. 2) <code>ADD HL,A</code>, <code>ADD</code> DE,A</code> and <code>ADD BC,A</code> most probably always reset the carry flag.

	=== Errata ===		=== Errata ===

Johnnyo: /* Errata */ removed an inconclusive old paragraph

2025-01-25T17:28:20Z

Errata: removed an inconclusive old paragraph

← Older revision		Revision as of 18:28, 25 January 2025
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	2022-01-11: The previous versions of this page didn't match what was [http://www.z80.info/zip/z80-documented.pdf documented] for several years, that regular Z80 INI/IND/INIR/INDR/OUTI/OUTD/OTIR/OTDR instructions do modify carry flag (contrary to the official Z80 documentation and many Internet resources describing Z80 instructions).		2022-01-11: The previous versions of this page didn't match what was [http://www.z80.info/zip/z80-documented.pdf documented] for several years, that regular Z80 INI/IND/INIR/INDR/OUTI/OUTD/OTIR/OTDR instructions do modify carry flag (contrary to the official Z80 documentation and many Internet resources describing Z80 instructions).

	2021-09-16: The Z80N-specific instructions <code>ADD HL,A</code>, <code>ADD DE,A</code> and <code>ADD BC,A</code> '''do not preserve carry flag''', but change it to an undefined value (confirmed by the tests by Ped on the core 3.1.5). (Note: That behaviour could change in the later cores)

← Older revision		Revision as of 15:03, 17 January 2026
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	! Instruction !!data-sort-type="text"\| Encoding (2-4 bytes) (hex) !! T-States !! Description !! 4 letter		! Instruction !!data-sort-type="text"\| Encoding (2-4 bytes) (hex) !! T-States !! Description !! 4 letter
	\|-		\|-
	\|~~<code>~~ <code>SWAPNIB~~</code>~~ </code>\|\| <code>ED 23</code> \|\| 8 \|\| Swap the nibbles (4-bits) of A \|\| SWAP		\|<code>SWAPNIB</code>\|\| <code>ED 23</code> \|\| 8 \|\| Swap the nibbles (4-bits) of A \|\| SWAP
	\|-		\|-
	\|~~<code>~~ <code>MIRROR A~~</code>~~ </code>\|\| <code>ED 24</code> \|\| 8 \|\| Mirror bits 0..7 to 7..0 of A \|\| MIRR		\|<code>MIRROR A</code>\|\| <code>ED 24</code> \|\| 8 \|\| Mirror bits 0..7 to 7..0 of A \|\| MIRR
	\|-		\|-
	\|~~<code>~~ <code>TEST $im8~~</code>~~ </code>\|\| <code>ED 27</code> ~~value~~ \|\| 11 \|\| Change flags as AND A but A stays unaffected \|\|style="color:DarkGrey;"\| TEST		\|<code>TEST $im8</code>\|\| <code>ED 27 value</code> \|\| 11 \|\| Change flags as AND A but A stays unaffected \|\|style="color:DarkGrey;"\| TEST
	\|-		\|-
	\|~~<code>~~ <code>BSLA DE,B~~</code>~~ </code>\|\| <code>ED 28</code> \|\| 8 \|\| Shift left DE for B bits \|\|style="color:DarkGrey;"\| BSLA		\|<code>BSLA DE,B</code>\|\| <code>ED 28</code> \|\| 8 \|\| Shift left DE for B bits \|\|style="color:DarkGrey;"\| BSLA
	\|-		\|-
	\|~~<code>~~ <code>BSRA DE,B~~</code>~~ </code>\|\| <code>ED 29</code> \|\| 8 \|\| Shift right signed DE for B bits \|\|style="color:DarkGrey;"\| BSRA		\|<code>BSRA DE,B</code>\|\| <code>ED 29</code> \|\| 8 \|\| Shift right signed DE for B bits \|\|style="color:DarkGrey;"\| BSRA
	\|-		\|-
	\|~~<code>~~ <code>BSRL DE,B~~</code>~~ </code>\|\| <code>ED 2A</code> \|\| 8 \|\| Shift right DE for B bits \|\|style="color:DarkGrey;"\| BSRL		\|<code>BSRL DE,B</code>\|\| <code>ED 2A</code> \|\| 8 \|\| Shift right DE for B bits \|\|style="color:DarkGrey;"\| BSRL
	\|-		\|-
	\|~~<code>~~ <code>BSRF DE,B~~</code>~~ </code>\|\| <code>ED 2B</code> \|\| 8 \|\| Shift right DE, filling 1 for B bits \|\|style="color:DarkGrey;"\| BSRF		\|<code>BSRF DE,B</code>\|\| <code>ED 2B</code> \|\| 8 \|\| Shift right DE, filling 1 for B bits \|\|style="color:DarkGrey;"\| BSRF
	\|-		\|-
	\|~~<code>~~ <code>BRLC DE,B~~</code>~~ </code>\|\| <code>ED 2C</code> \|\| 8 \|\| Rotate left DE for B bits \|\|style="color:DarkGrey;"\| BRLC		\|<code>BRLC DE,B</code>\|\| <code>ED 2C</code> \|\| 8 \|\| Rotate left DE for B bits \|\|style="color:DarkGrey;"\| BRLC
	\|-		\|-
	\|~~<code>~~ <code>MUL D,E~~</code>~~ </code>\|\| <code>ED 30</code> \|\| 8 \|\| Multiply D with E, result in DE \|\|style="color:DarkGrey;"\| MUL		\|<code>MUL D,E</code>\|\| <code>ED 30</code> \|\| 8 \|\| Multiply D with E, result in DE \|\|style="color:DarkGrey;"\| MUL
	\|-		\|-
	\|~~<code>~~ <code>ADD HL,A~~</code>~~ </code>\|\| <code>ED 31</code> \|\| 8 \|\| Add unsigned A to HL \|\|style="color:DarkGrey;"\| ADD		\|<code>ADD HL,A</code>\|\| <code>ED 31</code> \|\| 8 \|\| Add unsigned A to HL \|\|style="color:DarkGrey;"\| ADD
	\|-		\|-
	\|~~<code>~~ <code>ADD DE,A~~</code>~~ </code>\|\| <code>ED 32</code> \|\| 8 \|\| Add unsigned A to DE \|\|style="color:DarkGrey;"\| ADD		\|<code>ADD DE,A</code>\|\| <code>ED 32</code> \|\| 8 \|\| Add unsigned A to DE \|\|style="color:DarkGrey;"\| ADD
	\|-		\|-
	\|~~<code>~~ <code>ADD BC,A~~</code>~~ </code>\|\| <code>ED 33</code> \|\| 8 \|\| Add unsigned A to BC \|\|style="color:DarkGrey;"\| ADD		\|<code>ADD BC,A</code>\|\| <code>ED 33</code> \|\| 8 \|\| Add unsigned A to BC \|\|style="color:DarkGrey;"\| ADD
	\|-		\|-
	\|~~<code>~~ <code>ADD HL,$im16~~</code>~~ </code>\|\| <code>ED 34 low high</code> \|\| 16 \|\| Add a constant to HL \|\|style="color:DarkGrey;"\| ADD		\|<code>ADD HL,$im16</code>\|\| <code>ED 34 low high</code> \|\| 16 \|\| Add a constant to HL \|\|style="color:DarkGrey;"\| ADD
	\|-		\|-
	\|~~<code>~~ <code>ADD DE,$im16~~</code>~~ </code>\|\| <code>ED 35 low high</code> \|\| 16 \|\| Add a constant to DE \|\|style="color:DarkGrey;"\| ADD		\|<code>ADD DE,$im16</code>\|\| <code>ED 35 low high</code> \|\| 16 \|\| Add a constant to DE \|\|style="color:DarkGrey;"\| ADD
	\|-		\|-
	\|~~<code>~~ <code>ADD BC,$im16~~</code>~~ </code>\|\| <code>ED 36 low high</code> \|\| 16 \|\| Add a constant to BC \|\|style="color:DarkGrey;"\| ADD		\|<code>ADD BC,$im16</code>\|\| <code>ED 36 low high</code> \|\| 16 \|\| Add a constant to BC \|\|style="color:DarkGrey;"\| ADD
	\|-		\|-
	\|~~<code>~~ <code>PUSH $im16~~</code>~~ </code>\|\| <code>ED 8A high low</code> \|\| 23 \|\| Push a constant \|\|style="color:DarkGrey;"\| PUSH		\|<code>PUSH $im16</code>\|\| <code>ED 8A high low</code> \|\| 23 \|\| Push a constant \|\|style="color:DarkGrey;"\| PUSH
	\|-		\|-
	\|~~<code>~~ <code>OUTINB~~</code>~~ </code>\|\| <code>ED 90</code> \|\| 16 \|\| OUTI, but don't change B \|\| OTIB		\|<code>OUTINB</code>\|\| <code>ED 90</code> \|\| 16 \|\| OUTI, but don't change B \|\| OTIB
	\|-		\|-
	\|~~<code>~~ <code>NEXTREG $im8,$im8~~</code>~~ </code>\|\| <code>ED 91 register value</code> \|\| 20 \|\| Write v to Next register r \|\| NREG		\|<code>NEXTREG $im8,$im8</code>\|\| <code>ED 91 register value</code> \|\| 20 \|\| Write v to Next register r \|\| NREG
	\|-		\|-
	\|~~<code>~~ <code>NEXTREG $im8,A~~</code>~~ </code>\|\| <code>ED 92 register</code> \|\| 17 \|\| Write A to Next register r \|\| NREG		\|<code>NEXTREG $im8,A</code>\|\| <code>ED 92 register</code> \|\| 17 \|\| Write A to Next register r \|\| NREG
	\|-		\|-
	\|~~<code>~~ <code>PIXELDN~~</code>~~ </code>\|\| <code>ED 93</code> \|\| 8 \|\| HL as a pixel address moved one line down \|\| PXDN		\|<code>PIXELDN</code>\|\| <code>ED 93</code> \|\| 8 \|\| HL as a pixel address moved one line down \|\| PXDN
	\|-		\|-
	\|~~<code>~~ <code>PIXELAD~~</code>~~ </code>\|\| <code>ED 94</code> \|\| 8 \|\| HL := as ULA pixel address from D==Y E==X \|\| PXAD		\|<code>PIXELAD</code>\|\| <code>ED 94</code> \|\| 8 \|\| HL := as ULA pixel address from D==Y E==X \|\| PXAD
	\|-		\|-
	\|~~<code>~~ <code>SETAE~~</code>~~ </code>\|\| <code>ED 95</code> \|\| 8 \|\| Get A as a mask for ULA pixel from E \|\| STAE		\|<code>SETAE</code>\|\| <code>ED 95</code> \|\| 8 \|\| Get A as a mask for ULA pixel from E \|\| STAE
	\|-		\|-
	\|~~<code>~~ <code>JP (C)~~</code>~~ </code>\|\| <code>ED 98</code> \|\| 13 \|\| IN (C) then jump to a 64 byte section \|\|style="color:DarkGrey;"\| JP		\|<code>JP (C)</code>\|\| <code>ED 98</code> \|\| 13 \|\| IN (C) then jump to a 64 byte section \|\|style="color:DarkGrey;"\| JP
	\|-		\|-
	\|~~<code>~~ <code>LDIX~~</code>~~ </code>\|\| <code>ED A4</code> \|\| 16 \|\| Extended LDI byte copy \|\|style="color:DarkGrey;"\| LDIX		\|<code>LDIX</code>\|\| <code>ED A4</code> \|\| 16 \|\| Extended LDI byte copy \|\|style="color:DarkGrey;"\| LDIX
	\|-		\|-
	\|~~<code>~~ <code>LDWS~~</code>~~ </code>\|\| <code>ED A5</code> \|\| 14 \|\| Byte copy as for Layer 2 \|\|style="color:DarkGrey;"\| LDWS		\|<code>LDWS</code>\|\| <code>ED A5</code> \|\| 14 \|\| Byte copy as for Layer 2 \|\|style="color:DarkGrey;"\| LDWS
	\|-		\|-
	\|~~<code>~~ <code>LDDX~~</code>~~ </code>\|\| <code>ED AC</code> \|\| 16 \|\| Extended LDD byte copy \|\|style="color:DarkGrey;"\| LDDX		\|<code>LDDX</code>\|\| <code>ED AC</code> \|\| 16 \|\| Extended LDD byte copy \|\|style="color:DarkGrey;"\| LDDX
	\|-		\|-
	\|~~<code>~~ <code>LDIRX~~</code>~~ </code>\|\| <code>ED B4</code> \|\| 21/16 \|\| Extended LDIR \|\| LIRX		\|<code>LDIRX</code>\|\| <code>ED B4</code> \|\| 21/16 \|\| Extended LDIR \|\| LIRX
	\|-		\|-
	\|~~<code>~~ <code>LDPIRX~~</code>~~ </code>\|\| <code>ED B7</code> \|\| 21/16 \|\| Byte copy as for a pattern fill \|\| LPRX		\|<code>LDPIRX</code>\|\| <code>ED B7</code> \|\| 21/16 \|\| Byte copy as for a pattern fill \|\| LPRX
	\|-		\|-
	\|~~<code>~~ <code>LDDRX~~</code>~~ </code>\|\| <code>ED BC</code> \|\| 21/16 \|\| Extended LDDR \|\| LDRX		\|<code>LDDRX</code>\|\| <code>ED BC</code> \|\| 21/16 \|\| Extended LDDR \|\| LDRX
	\|}		\|}