View source for Extended Z80 instruction set


This is a general list of Z80 instructions with descriptions. For summaries, you can view the [[Z80 Instruction Table]].

=== Term references ===
* ''Any 8-bit register'' means A, B, C, D, E, H, and L. F, I and R do not count even though they are technically 8 bit registers. Also, the high and low bytes of IX and IY (IXH, IXL, IYH, IYL) can be used as 8-bit registers although this behavior was undocumented on the original Z80.
* IXY means IX or IY.
* For the status field:
** S means Standard. It's in the Z80 manual. Everything should support it.
** U means Undocumented. It works on Z80 chips, but it's not in the manual. These have been known for years and were acknowledged by Zilog, so they should work on everything, but some assemblers may vary the syntax.
** E means Extension. It ''only'' works on the Z80 core on the Next. It'll probably only be accepted by assemblers that have been updated specifically for the Next.
* Each of the flag effects is documented as follows:
** - means the flag is unchanged.
** 1 or 0 mean the flag is set or reset as appropriate.
** ? means we don't know what effect the instruction has on the flag.
** ! means the instruction has an unusual effect on the flag which is documented in the description.
** S means the effect on the flag is "standard". C is set if a carry/borrow occurred beyond the MSB; Z is set if the result of the operation is zero; H is set if a carry/borrow occurred beyond bit 3.
** P, V, and L are used for the P/V flag which has several standard effects. P means it's parity. V means it's overflow. L means it detects the end of a loop (BC reaching 0) as it does for some of the block copy and search instructions.

=== Register and Data manipulation ===
;LD (LoaD)

:{{Opcodelisttop}}
{{Opcode|opdesc=LD r, r'
 |ad1=Register
 |ad2=Register
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=4
}}

{{Opcode|opdesc=LD r,n
 |ad1=Register
 |ad2=Immediate
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=7
}}

{{Opcode|opdesc=LD r, (HL)
 |ad1=Register
 |ad2=Indirect
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=7
}}

{{Opcode|opdesc=LD r, (IXY+d)
 |ad1=Register
 |ad2=Indexed
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=19
}}

{{Opcode|opdesc=LD (HL),r
 |ad1=Indirect
 |ad2=Register
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=7
}}

{{Opcode|opdesc=LD (IXY+d),r
 |ad1=Indexed
 |ad2=Register
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=19
}}

{{Opcode|opdesc=LD (HL), n
 |ad1=Indirect
 |ad2=Immediate
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=10
}}

{{Opcode|opdesc=LD (IXY+d), n
 |ad1=Indexed
 |ad2=Immediate
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=19
}}

{{Opcode|opdesc=LD A, (BC/DE)
 |ad1=Accumulator
 |ad2=Indirect
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=7
}}

{{Opcode|opdesc=LD A, (nn)
 |ad1=Accumulator
 |ad2=Address
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=13
}}

{{Opcode|opdesc=LD (BC/DE), A
 |ad1=Indirect
 |ad2=Accumulator
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=7
}}


{{Opcode|opdesc=LD (nn), A
 |ad1=Address
 |ad2=Accumulator
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=13
}}

{{Opcode|opdesc=LD A, I
 |ad1=Accumulator
 |ad2=Register
 |status=S
 |c=-
 |n=0
 |pv=!
 |h=0
 |z=S
 |s=S
 |tstates=9
}}

{{Opcode|opdesc=LD A, R
 |ad1=Accumulator
 |ad2=Register
 |status=S
 |c=-
 |n=0
 |pv=!
 |h=0
 |z=S
 |s=S
 |tstates=9
}}

{{Opcode|opdesc=LD I, A
 |ad1=Register
 |ad2=Accumulator
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=9
}}


{{Opcode|opdesc=LD R, A
 |ad1=Register
 |ad2=Accumulator
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=9
}}

{{Opcode|opdesc=LD BC/DE/HL/SP, nn
 |ad1=Register
 |ad2=Immediate
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=10
}}


{{Opcode|opdesc=LD IXY, nn
 |ad1=Register
 |ad2=Immediate
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=14
}}


{{Opcode|opdesc=LD HL, (nn)
 |ad1=Register
 |ad2=Address
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=16
}}


{{Opcode|opdesc=LD BC/DE/SP/IXY, (nn)
 |ad1=Register
 |ad2=Address
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=20
}}


{{Opcode|opdesc=LD (nn), HL
 |ad1=Address
 |ad2=Register
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=16
}}

{{Opcode|opdesc=LD (nn), HL
 |ad1=Address
 |ad2=Register
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=16
}}

{{Opcode|opdesc=LD (nn), BC/DE/SP/IXY
 |ad1=Address
 |ad2=Register
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=20
}}

{{Opcode|opdesc=LD SP, HL
 |ad1=Address
 |ad2=Register
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=6
}}

{{Opcode|opdesc=LD SP, IXY
 |ad1=Register
 |ad2=Register
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=10
}}
|}
:The basic data load/transfer instruction. Transfers data from the location specified by the second argument, to the location specified by the first. Available combinations are as follows:
:* Any 8-bit register can be:
:** loaded with an immediate value;
:** loaded with the contents of any other 8-bit register except I and R;
:** loaded with the contents of, or stored in, memory pointed to by HL;
:** loaded with the contents of, or stored in, memory offset-indexed by IX or IY.
:* Additionally, the accumulator A (only) can be:
:** loaded with the contents of, or stored in, memory pointed to by BC or DE;
:** loaded with the contents of, or stored in, memory pointed to by an immediate address;
:** loaded with the contents of I or R.
:* Any 16-bit register pair can be:
:** loaded with an immediate value;
:** loaded with the contents of, or stored in, memory pointed to by an immediate address.
:* Additionally, SP (only) can be:
:** loaded with the contents of HL, IX, or IY.
:* Memory referred to by HL or through IX can be assigned immediate values.
:Although 16-bit register pairs cannot be directly moved between each other, they can be moved by moving the two 8-bit registers. (SP gets a special case because it can't be addressed via 8-bit registers.) Some assemblers will provide built-in macro instructions allowing, for example, '''ld bc, de'''.
:LD instructions do not alter any flags unless I or R are loaded into A.


;EX (EXchange)
:{{Opcodelisttop}}
{{Opcode|opdesc=EX DE, HL
 |ad1=Register
 |ad2=Register
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=4
}}
{{Opcode|opdesc=EX AF, AF'
 |ad1=Register
 |ad2=Register
 |status=S
 |c=!
 |n=!
 |pv=!
 |h=!
 |z=!
 |s=!
 |tstates=4
}}
{{Opcode|opdesc=EX (SP), HL
 |ad1=Indirect
 |ad2=Register
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=19
}}
{{Opcode|opdesc=EX (SP), IXY
 |ad1=Indirect
 |ad2=Register
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=23
}}
|}
:Exchanges the contents of two sources. The only permitted combinations are
:* Exchanging DE and HL;
:* Exchanging AF and AF';
:* Exchanging HL, IX, or IY with the contents of memory pointed to by SP.


;EXX (EXchange all)
:{{Opcodelisttop}}
{{Opcode|opdesc=EXX
 |ad1=-
 |ad2=-
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=4
}}
|}
:Exchanges BC, DE, and HL with their shadow registers. AF and AF' are not exchanged. 



;PUSH
:{{Opcodelisttop}}
{{Opcode|opdesc=PUSH BC/DE/HL/AF
 |ad1=Register
 |ad2=-
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=11
}}
{{Opcode|opdesc=PUSH IXY
 |ad1=Register
 |ad2=-
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=15
}}
|}
:Pushes the given argument on the stack. This can be any 16-bit register pair except SP. SP is reduced by 2 and then the argument is written to the new location SP points to.



;POP
:{{Opcodelisttop}}
{{Opcode|opdesc=POP BC/DE/HL/AF
 |ad1=Register
 |ad2=-
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=10
}}
{{Opcode|opdesc=POP IXY
 |ad1=Register
 |ad2=-
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=14
}}
|}
:Pops the given argument from the stack. This can be any 16-bit register pair except SP. The current value at SP is copied to the register pair and then SP is raised by 2.

=== Block Copy ===
;LDI (LoaD and Increment)
:{{Opcodelisttop}}
{{Opcode|opdesc=LDI
 |ad1=-
 |ad2=-
 |status=S
 |c=-
 |n=0
 |pv=L
 |h=0
 |z=-
 |s=-
 |tstates=16
}}
|}
:Copies the byte pointed to by HL to the address pointed to by DE, then adds 1 to DE and HL and subtracts 1 from BC. If BC did not reach 0, P/V is reset, otherwise it is set. 


;LDIR (LoaD and Increment Repeated)
:{{Opcodelisttop}}
{{Opcode|opdesc=LDIR
 |ad1=-
 |ad2=-
 |status=S
 |c=-
 |n=0
 |pv=L
 |h=0
 |z=-
 |s=-
 |tstates=21x+16
}}
|}
:Automatically loops LDI until BC reaches zero. Note that no loop occurs with BC=0. Flag effects are the same as LDI except that P/V will always be set, because BC by definition reaches 0 before this instruction ends.



;LDD (LoaD and Decrement)
:{{Opcodelisttop}}
{{Opcode|opdesc=LDD
 |ad1=-
 |ad2=-
 |status=S
 |c=-
 |n=0
 |pv=L
 |h=0
 |z=-
 |s=-
 |tstates=16
}}
|}
:Same as LDI, but subtracts 1 from DE and HL instead of adding.



;LDDR (LoaD and Decrement Repeated)
:{{Opcodelisttop}}
{{Opcode|opdesc=LDDR
 |ad1=-
 |ad2=-
 |status=S
 |c=-
 |n=0
 |pv=0
 |h=0
 |z=-
 |s=-
 |tstates=21
}}
|}
:Same as LDIR but loops LDD instead of LDI.



;LDIX, LDIRX, LDDX, LDDRX
:{{Opcodelisttop}}
{{Opcode|opdesc=LDIX
 |ad1=-
 |ad2=-
 |status=E
 |c=?
 |n=?
 |pv=?
 |h=?
 |z=?
 |s=?
 |tstates=?
}}
{{Opcode|opdesc=LDIRX
 |ad1=-
 |ad2=-
 |status=E
 |c=?
 |n=?
 |pv=?
 |h=?
 |z=?
 |s=?
 |tstates=?
}}
{{Opcode|opdesc=LDDX
 |ad1=-
 |ad2=-
 |status=E
 |c=?
 |n=?
 |pv=?
 |h=?
 |z=?
 |s=?
 |tstates=?
}}
{{Opcode|opdesc=LDDRX
 |ad1=-
 |ad2=-
 |status=E
 |c=?
 |n=?
 |pv=?
 |h=?
 |z=?
 |s=?
 |tstates=?
}}
|}
:Next-only extended opcodes. Behave the same as their non-X equivalents except the byte is not copied if it is equal to A.



=== Block Search ===
;CPI (ComPare and Increment)
:{{Opcodelisttop}}
{{Opcode|opdesc=CPI
 |ad1=-
 |ad2=-
 |status=S
 |c=-
 |n=1
 |pv=L
 |h=S
 |z=!
 |s=S
 |tstates=16
}}
|}
:Compares the byte pointed to by HL with the contents of A and sets Z if it matches or S if the comparison goes negative. Then adds 1 to HL and subtracts 1 from BC. Sets P/V if BC did not reach 0 or resets it if it did. 



;CPIR (ComPare and Increment Repeated)
:{{Opcodelisttop}}
{{Opcode|opdesc=CPIR
 |ad1=-
 |ad2=-
 |status=S
 |c=-
 |n=1
 |pv=L
 |h=S
 |z=!
 |s=S
 |tstates=21x+16
}}
|}
:Automatically loops CPI until either Z is set (A is found in the byte pointed to by HL) or P/V is reset (BC reached 0). Flag effects are the same as CPI except that one of the two terminating flag conditions will always be true.



;CPD (ComPare and Decrement)
:{{Opcodelisttop}}
{{Opcode|opdesc=CPD
 |ad1=-
 |ad2=-
 |status=S
 |c=-
 |n=1
 |pv=L
 |h=S
 |z=!
 |s=S
 |tstates=16
}}
|}
:Same as CPI, but subtracts 1 from HL instead of adding it.



;CPDR (ComPare and Decrement Repeated)
:{{Opcodelisttop}}
{{Opcode|opdesc=CPDR
 |ad1=-
 |ad2=-
 |status=S
 |c=-
 |n=1
 |pv=L
 |h=S
 |z=!
 |s=S
 |tstates=21x+16
}}
|}
:Same as CPIR but loops CPD instead of CPI. 



=== Arithmetic ===
;ADD
:{{Opcodelisttop}}
{{Opcode|opdesc=ADD A, r
 |ad1=Accumulator
 |ad2=Register
 |status=S
 |c=S
 |n=0
 |pv=V
 |h=S
 |z=S
 |s=S
 |tstates=4
}}
{{Opcode|opdesc=ADD A, n
 |ad1=Accumulator
 |ad2=Immediate
 |status=S
 |c=S
 |n=0
 |pv=V
 |h=S
 |z=S
 |s=S
 |tstates=7
}}
{{Opcode|opdesc=ADD A, (HL)
 |ad1=Accumulator
 |ad2=Indirect
 |status=S
 |c=S
 |n=0
 |pv=V
 |h=S
 |z=S
 |s=S
 |tstates=7
}}
{{Opcode|opdesc=ADD A, (IXY+d)
 |ad1=Accumulator
 |ad2=Indexed
 |status=S
 |c=S
 |n=0
 |pv=V
 |h=S
 |z=S
 |s=S
 |tstates=19
}}
{{Opcode|opdesc=ADD HL, BC/DE/HL/SP
 |ad1=Register
 |ad2=Register
 |status=S
 |c=S
 |n=0
 |pv=-
 |h=!
 |z=-
 |s=-
 |tstates=11
}}
{{Opcode|opdesc=ADD IXY, BC/DE/IXY/SP
 |ad1=Register
 |ad2=Register
 |status=S
 |c=S
 |n=0
 |pv=-
 |h=!
 |z=-
 |s=-
 |tstates=15
}}
{{Opcode|opdesc=ADD HL/DE/BC, A
 |ad1=Register
 |ad2=Register
 |status=E
 |c=?
 |n=?
 |pv=?
 |h=?
 |z=?
 |s=?
 |tstates=?
}}
|}
{{Opcode|opdesc=ADD HL/DE/BC, nnnn
 |ad1=Register
 |ad2=Immediate
 |status=E
 |c=?
 |n=?
 |pv=?
 |h=?
 |z=?
 |s=?
 |tstates=?
}}
|}
:Adds values together. Legal combinations are:
:* When adding 8-bit values the first parameter must be A and the second may be:
:** The contents of an 8-bit register;
:** An immediate value;
:** The contents of memory pointed to by HL or by indexing based on IX or IY.
:* When adding 16-bit values the first parameter must be HL, IX or IY and the second must be another 16-bit register pair. If the first parameter is IX or IY, the second cannot be HL or the other index register. 
:* On the Spectrum Next the extended opcodes also allow the first parameter to be HL, DE, or BC and the second to be A or an immediate value.
:For 16 bit additions, H is set if a carry occurred in bit 11 (ie, a half carry in the high byte)


;ADC (ADd with Carry)
:{{Opcodelisttop}}
{{Opcode|opdesc=ADC A, r
 |ad1=Accumulator
 |ad2=Register
 |status=S
 |c=S
 |n=0
 |pv=V
 |h=S
 |z=S
 |s=S
 |tstates=4
}}
{{Opcode|opdesc=ADC A, n
 |ad1=Accumulator
 |ad2=Immediate
 |status=S
 |c=S
 |n=0
 |pv=V
 |h=S
 |z=S
 |s=S
 |tstates=7
}}
{{Opcode|opdesc=ADC A, (HL)
 |ad1=Accumulator
 |ad2=Indirect
 |status=S
 |c=S
 |n=0
 |pv=V
 |h=S
 |z=S
 |s=S
 |tstates=7
}}
{{Opcode|opdesc=ADC A, (IXY+d)
 |ad1=Accumulator
 |ad2=Indexed
 |status=S
 |c=S
 |n=0
 |pv=V
 |h=S
 |z=S
 |s=S
 |tstates=19
}}
{{Opcode|opdesc=ADC HL, BC/DE/HL/SP
 |ad1=Register
 |ad2=Register
 |status=S
 |c=S
 |n=0
 |pv=-
 |h=!
 |z=-
 |s=-
 |tstates=15
}}
|}
:Adds values together, adding an additional 1 if Carry is set. Legal combinations are the same as for ADD, although there are no extended opcode versions of ADC and in 16-bit values the first parameter can only be HL. 

 

;SUB
:{{Opcodelisttop}}
{{Opcode|opdesc=SUB r
 |ad1=Register
 |ad2=-
 |status=S
 |c=S
 |n=0
 |pv=V
 |h=S
 |z=S
 |s=S
 |tstates=4
}}
{{Opcode|opdesc=SUB n
 |ad1=Immediate
 |ad2=-
 |status=S
 |c=S
 |n=0
 |pv=V
 |h=S
 |z=S
 |s=S
 |tstates=7
}}
{{Opcode|opdesc=SUB (HL)
 |ad1=Indirect
 |ad2=-
 |status=S
 |c=S
 |n=0
 |pv=V
 |h=S
 |z=S
 |s=S
 |tstates=7
}}
{{Opcode|opdesc=SUB (IXY+d)
 |ad1=Indexed
 |ad2=-
 |status=S
 |c=S
 |n=0
 |pv=V
 |h=S
 |z=S
 |s=S
 |tstates=19
}}
|}
:Subtracts a value from A. Legal combinations are the same as for ADD for 8-bit, except that A does not need to be specified as the first parameter because subtraction can only be done from A. SUB cannot be used for 16-bit numbers. 



;SBC (SuBtract with Carry, er, borrow)
:{{Opcodelisttop}}
{{Opcode|opdesc=SBC A, r
 |ad1=Accumulator
 |ad2=Register
 |status=S
 |c=S
 |n=0
 |pv=V
 |h=S
 |z=S
 |s=S
 |tstates=4
}}
{{Opcode|opdesc=SBC A, n
 |ad1=Accumulator
 |ad2=Immediate
 |status=S
 |c=S
 |n=0
 |pv=V
 |h=S
 |z=S
 |s=S
 |tstates=7
}}
{{Opcode|opdesc=SBC A, (HL)
 |ad1=Accumulator
 |ad2=Indirect
 |status=S
 |c=S
 |n=0
 |pv=V
 |h=S
 |z=S
 |s=S
 |tstates=7
}}
{{Opcode|opdesc=SBC A, (IXY+d)
 |ad1=Accumulator
 |ad2=Indexed
 |status=S
 |c=S
 |n=0
 |pv=V
 |h=S
 |z=S
 |s=S
 |tstates=19
}}
{{Opcode|opdesc=SBC HL, BC/DE/HL/SP
 |ad1=Register
 |ad2=Register
 |status=S
 |c=S
 |n=0
 |pv=-
 |h=!
 |z=-
 |s=-
 |tstates=15
}}
|}
:Subtracts values, subtracting an additional 1 if Carry is set. Legal combinations are the same as for ADD, although there are no extended opcode versions of SBC and in 16-bit values the first parameter can only be HL. 



;AND, OR, XOR
:{{Opcodelisttop}}
{{Opcode|opdesc=AND r
 |ad1=Register
 |ad2=-
 |status=S
 |c=0
 |n=0
 |pv=V
 |h=1
 |z=S
 |s=S
 |tstates=4
}}
{{Opcode|opdesc=AND n
 |ad1=Immediate
 |ad2=-
 |status=S
 |c=0
 |n=0
 |pv=V
 |h=1
 |z=S
 |s=S
 |tstates=7
}}
{{Opcode|opdesc=AND (HL)
 |ad1=Indirect
 |ad2=-
 |status=S
 |c=0
 |n=0
 |pv=V
 |h=1
 |z=S
 |s=S
 |tstates=7
}}
{{Opcode|opdesc=AND (IXY+d)
 |ad1=Indexed
 |ad2=-
 |status=S
 |c=0
 |n=0
 |pv=V
 |h=1
 |z=S
 |s=S
 |tstates=19
}}
{{Opcode|opdesc=OR r
 |ad1=Register
 |ad2=-
 |status=S
 |c=0
 |n=0
 |pv=V
 |h=0
 |z=S
 |s=S
 |tstates=4
}}
{{Opcode|opdesc=OR n
 |ad1=Immediate
 |ad2=-
 |status=S
 |c=0
 |n=0
 |pv=V
 |h=0
 |z=S
 |s=S
 |tstates=7
}}
{{Opcode|opdesc=OR (HL)
 |ad1=Indirect
 |ad2=-
 |status=S
 |c=0
 |n=0
 |pv=V
 |h=0
 |z=S
 |s=S
 |tstates=7
}}
{{Opcode|opdesc=OR (IXY+d)
 |ad1=Indexed
 |ad2=-
 |status=S
 |c=0
 |n=0
 |pv=V
 |h=0
 |z=S
 |s=S
 |tstates=19
}}
{{Opcode|opdesc=XOR r
 |ad1=Register
 |ad2=-
 |status=S
 |c=0
 |n=0
 |pv=P
 |h=0
 |z=S
 |s=S
 |tstates=4
}}
{{Opcode|opdesc=XOR n
 |ad1=Immediate
 |ad2=-
 |status=S
 |c=0
 |n=0
 |pv=P
 |h=0
 |z=S
 |s=S
 |tstates=7
}}
{{Opcode|opdesc=XOR (HL)
 |ad1=Indirect
 |ad2=-
 |status=S
 |c=0
 |n=0
 |pv=P
 |h=0
 |z=S
 |s=S
 |tstates=7
}}
{{Opcode|opdesc=XOR (IXY+d)
 |ad1=Indexed
 |ad2=-
 |status=S
 |c=0
 |n=0
 |pv=P
 |h=0
 |z=S
 |s=S
 |tstates=19
}}
|}
:Performs the appropriate bitwise operator on A. Legal combinations are the same as SUB. 



;CP (ComPare)
:{{Opcodelisttop}}
{{Opcode|opdesc=CP r
 |ad1=Register
 |ad2=-
 |status=S
 |c=S
 |n=1
 |pv=V
 |h=S
 |z=S
 |s=S
 |tstates=4
}}
{{Opcode|opdesc=CP n
 |ad1=Immediate
 |ad2=-
 |status=S
 |c=S
 |n=1
 |pv=V
 |h=S
 |z=S
 |s=S
 |tstates=7
}}
{{Opcode|opdesc=CP (HL)
 |ad1=Indirect
 |ad2=-
 |status=S
 |c=S
 |n=1
 |pv=V
 |h=S
 |z=S
 |s=S
 |tstates=7
}}
{{Opcode|opdesc=CP (IXY+d)
 |ad1=Indexed
 |ad2=-
 |status=S
 |c=S
 |n=1
 |pv=V
 |h=S
 |z=S
 |s=S
 |tstates=19
}}
|}
:Sets the flags as if a SUB was performed but does not perform it. Legal combinations are the same as SUB. This is commonly used to set the flags to perform an equality or greater/less test.
:* CP is ''not'' equivalent to "if" in high level languages. Flag based jumps can follow any instruction that sets the flags, not just CP.



;INC (INCrement)
:{{Opcodelisttop}}
{{Opcode|opdesc=INC r
 |ad1=Register
 |ad2=-
 |status=S
 |c=-
 |n=0
 |pv=!
 |h=S
 |z=S
 |s=S
 |tstates=4
}}
{{Opcode|opdesc=INC (HL)
 |ad1=Indirect
 |ad2=-
 |status=S
 |c=-
 |n=0
 |pv=!
 |h=S
 |z=S
 |s=S
 |tstates=11
}}
{{Opcode|opdesc=INC (IXY+d)
 |ad1=Indexed
 |ad2=-
 |status=S
 |c=-
 |n=0
 |pv=!
 |h=S
 |z=S
 |s=S
 |tstates=23
}}
{{Opcode|opdesc=INC BC/DE/HL/SP
 |ad1=Register
 |ad2=-
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=6
}}
{{Opcode|opdesc=INC IXY
 |ad1=Register
 |ad2=-
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=10
}}
|}
:Increments the target by one. The argument can be any 8-bit register, any 16-bit register pair, or the address pointed to by HL or indexed via IX or IY. P/V is set if the target held $7F. N is reset.
:* INC A is faster than ADD 1.


;DEC
:{{Opcodelisttop}}
{{Opcode|opdesc=DEC r
 |ad1=Register
 |ad2=-
 |status=S
 |c=-
 |n=1
 |pv=!
 |h=S
 |z=S
 |s=S
 |tstates=4
}}
{{Opcode|opdesc=DEC (HL)
 |ad1=Indirect
 |ad2=-
 |status=S
 |c=-
 |n=1
 |pv=!
 |h=S
 |z=S
 |s=S
 |tstates=11
}}
{{Opcode|opdesc=DEC (IXY+d)
 |ad1=Indexed
 |ad2=-
 |status=S
 |c=-
 |n=1
 |pv=!
 |h=S
 |z=S
 |s=S
 |tstates=23
}}
{{Opcode|opdesc=DEC BC/DE/HL/SP
 |ad1=Register
 |ad2=-
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=6
}}
{{Opcode|opdesc=DEC IXY
 |ad1=Register
 |ad2=-
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=10
}}
|}
:Decrements the target by one. Allowed arguments are the same as INC. Flag effects are the same as INC except H refers to borrow, not carry; and P/V is set if the target held $80.
:* DEC A is faster than SUB 1.


;RLC (Rotate Left and Copy)
:{{Opcodelisttop}}
{{Opcode|opdesc=RLC r
 |ad1=Register
 |ad2=-
 |status=S
 |c=!
 |n=0
 |pv=P
 |h=0
 |z=S
 |s=S
 |tstates=8
}}
{{Opcode|opdesc=RLC (HL)
 |ad1=Indirect
 |ad2=-
 |status=S
 |c=!
 |n=0
 |pv=P
 |h=0
 |z=S
 |s=S
 |tstates=15
}}
{{Opcode|opdesc=RLC (IXY+d)
 |ad1=Indexed
 |ad2=-
 |status=S
 |c=!
 |n=0
 |pv=P
 |h=0
 |z=S
 |s=S
 |tstates=23
}}
{{Opcode|opdesc=RLC r,(IX+d)
 |ad1=Register
 |ad2=Indexed
 |status=U
 |c=!
 |n=0
 |pv=P
 |h=0
 |z=S
 |s=S
 |tstates=?
}}
|}
:Rotates the target bitwise left by one position. The MSB is copied to bit 0, and also to Carry. Can be applied to any 8-bit register or to a location in memory pointed to by HL or indexed via IX or IY. The final alternative is undocumented, and stores the result in a register as well as performing the operation. 



;RL (Rotate Left)
:{{Opcodelisttop}}
{{Opcode|opdesc=RL r
 |ad1=Register
 |ad2=-
 |status=S
 |c=!
 |n=0
 |pv=P
 |h=0
 |z=S
 |s=S
 |tstates=8
}}
{{Opcode|opdesc=RL (HL)
 |ad1=Indirect
 |ad2=-
 |status=S
 |c=!
 |n=0
 |pv=P
 |h=0
 |z=S
 |s=S
 |tstates=15
}}
{{Opcode|opdesc=RL (IXY+d)
 |ad1=Indexed
 |ad2=-
 |status=S
 |c=!
 |n=0
 |pv=P
 |h=0
 |z=S
 |s=S
 |tstates=23
}}
{{Opcode|opdesc=RL r,(IX+d)
 |ad1=Register
 |ad2=Indexed
 |status=U
 |c=!
 |n=0
 |pv=P
 |h=0
 |z=S
 |s=S
 |tstates=?
}}

|}
:Same as RLC, except the MSB is copied to Carry only, and the previous contents of Carry are copied to bit 0.



;RRC, RR (Rotate Right and Copy, Rotate Right)
:{{Opcodelisttop}}
{{Opcode|opdesc=RRC r
 |ad1=Register
 |ad2=-
 |status=S
 |c=!
 |n=0
 |pv=P
 |h=0
 |z=S
 |s=S
 |tstates=8
}}
{{Opcode|opdesc=RRC (HL)
 |ad1=Indirect
 |ad2=-
 |status=S
 |c=!
 |n=0
 |pv=P
 |h=0
 |z=S
 |s=S
 |tstates=15
}}
{{Opcode|opdesc=RRC (IXY+d)
 |ad1=Indexed
 |ad2=-
 |status=S
 |c=!
 |n=0
 |pv=P
 |h=0
 |z=S
 |s=S
 |tstates=23
}}
{{Opcode|opdesc=RRC r,(IX+d)
 |ad1=Register
 |ad2=Indexed
 |status=U
 |c=!
 |n=0
 |pv=P
 |h=0
 |z=S
 |s=S
 |tstates=?
}}
{{Opcode|opdesc=RR r
 |ad1=Register
 |ad2=-
 |status=S
 |c=!
 |n=0
 |pv=P
 |h=0
 |z=S
 |s=S
 |tstates=8
}}
{{Opcode|opdesc=RR (HL)
 |ad1=Indirect
 |ad2=-
 |status=S
 |c=!
 |n=0
 |pv=P
 |h=0
 |z=S
 |s=S
 |tstates=15
}}
{{Opcode|opdesc=RR (IXY+d)
 |ad1=Indexed
 |ad2=-
 |status=S
 |c=!
 |n=0
 |pv=P
 |h=0
 |z=S
 |s=S
 |tstates=23
}}
{{Opcode|opdesc=RR r,(IX+d)
 |ad1=Register
 |ad2=Indexed
 |status=U
 |c=!
 |n=0
 |pv=P
 |h=0
 |z=S
 |s=S
 |tstates=?
}}
|}
:Same as RLC and RL except they rotate right instead of left.



;SLA (Shift Left Arithmetic)
:{{Opcodelisttop}}
{{Opcode|opdesc=SLA r
 |ad1=Register
 |ad2=-
 |status=S
 |c=!
 |n=0
 |pv=P
 |h=0
 |z=S
 |s=S
 |tstates=8
}}
{{Opcode|opdesc=SLA (HL)
 |ad1=Indirect
 |ad2=-
 |status=S
 |c=!
 |n=0
 |pv=P
 |h=0
 |z=S
 |s=S
 |tstates=15
}}
{{Opcode|opdesc=SLA (IXY+d)
 |ad1=Indexed
 |ad2=-
 |status=S
 |c=!
 |n=0
 |pv=P
 |h=0
 |z=S
 |s=S
 |tstates=23
}}
{{Opcode|opdesc=SLA r,(IX+d)
 |ad1=Register
 |ad2=Indexed
 |status=U
 |c=!
 |n=0
 |pv=P
 |h=0
 |z=S
 |s=S
 |tstates=?
}}
|}
:Same as RL except bit 0 is set to zero, not the previous contents of Carry.



;SRA (Shift Right Arithmetic)
:{{Opcodelisttop}}
{{Opcode|opdesc=SRA r
 |ad1=Register
 |ad2=-
 |status=S
 |c=!
 |n=0
 |pv=P
 |h=0
 |z=S
 |s=S
 |tstates=8
}}
{{Opcode|opdesc=SRA (HL)
 |ad1=Indirect
 |ad2=-
 |status=S
 |c=!
 |n=0
 |pv=P
 |h=0
 |z=S
 |s=S
 |tstates=15
}}
{{Opcode|opdesc=SRA (IXY+d)
 |ad1=Indexed
 |ad2=-
 |status=S
 |c=!
 |n=0
 |pv=P
 |h=0
 |z=S
 |s=S
 |tstates=23
}}
{{Opcode|opdesc=SRA r,(IX+d)
 |ad1=Register
 |ad2=Indexed
 |status=U
 |c=!
 |n=0
 |pv=P
 |h=0
 |z=S
 |s=S
 |tstates=?
}}
|}
:Same as RR except the MSB is left unchanged (on the assumption that it's the sign bit), not replaced with the previous contents of Carry. 



;SRL (Shift Right Logical)
:{{Opcodelisttop}}
{{Opcode|opdesc=SRL r
 |ad1=Register
 |ad2=-
 |status=S
 |c=!
 |n=0
 |pv=P
 |h=0
 |z=S
 |s=0
 |tstates=8
}}
{{Opcode|opdesc=SRL (HL)
 |ad1=Indirect
 |ad2=-
 |status=S
 |c=!
 |n=0
 |pv=P
 |h=0
 |z=S
 |s=0
 |tstates=15
}}
{{Opcode|opdesc=SRL (IXY+d)
 |ad1=Indexed
 |ad2=-
 |status=S
 |c=!
 |n=0
 |pv=P
 |h=0
 |z=S
 |s=0
 |tstates=23
}}
{{Opcode|opdesc=SRL r,(IX+d)
 |ad1=Register
 |ad2=Indexed
 |status=U
 |c=!
 |n=0
 |pv=P
 |h=0
 |z=S
 |s=0
 |tstates=?
}}
|}
:Same as SLA except it shifts right instead of left.



;RLCA, RLA, RRCA, RRA
:{{Opcodelisttop}}
{{Opcode|opdesc=RLCA
 |ad1=-
 |ad2=-
 |status=S
 |c=!
 |n=0
 |pv=-
 |h=0
 |z=-
 |s=-
 |tstates=4
}}
{{Opcode|opdesc=RLA
 |ad1=-
 |ad2=-
 |status=S
 |c=!
 |n=0
 |pv=-
 |h=0
 |z=-
 |s=-
 |tstates=4
}}
{{Opcode|opdesc=RRCA
 |ad1=-
 |ad2=-
 |status=S
 |c=!
 |n=0
 |pv=-
 |h=0
 |z=-
 |s=-
 |tstates=4
}}
{{Opcode|opdesc=RRA
 |ad1=-
 |ad2=-
 |status=S
 |c=!
 |n=0
 |pv=-
 |h=0
 |z=-
 |s=-
 |tstates=4
}}
|}
:Same as their matching instruction except they work only on A, are faster, and do not alter S, Z or P/V.



;SLL (Shift Left Logical)
:This mnemonic has no associated opcode. There is no difference between a logical and arithmetic shift left, so both can use SLA, but some assemblers will allow SLL as an equivalent. Unfortunately, some will also assemble it as SL1. So it's probably worth just avoiding.



;SL1 (Shift Left and Add 1)
:{{Opcodelisttop}}
{{Opcode|opdesc=SL1 r
 |ad1=Register
 |ad2=-
 |status=U
 |c=!
 |n=0
 |pv=P
 |h=0
 |z=S
 |s=S
 |tstates=8
}}
{{Opcode|opdesc=SL1 (HL)
 |ad1=Indirect
 |ad2=-
 |status=U
 |c=!
 |n=0
 |pv=P
 |h=0
 |z=S
 |s=S
 |tstates=15
}}
{{Opcode|opdesc=SL1 (IXY+d)
 |ad1=Indexed
 |ad2=-
 |status=U
 |c=!
 |n=0
 |pv=P
 |h=0
 |z=S
 |s=S
 |tstates=23
}}
{{Opcode|opdesc=SL1 r,(IX+d)
 |ad1=Register
 |ad2=Indexed
 |status=U
 |c=!
 |n=0
 |pv=P
 |h=0
 |z=S
 |s=S
 |tstates=?
}}
|}
:Undocumented opcodes that behave like SLA, but set bit 0 to 1 instead of 0.



;RLD
:{{Opcodelisttop}}
{{Opcode|opdesc=RLD
 |ad1=-
 |ad2=-
 |status=S
 |c=-
 |n=0
 |pv=P
 |h=0
 |z=S
 |s=S
 |tstates=18
}}
|}
:Rotates the lower nibble of the byte pointed to by HL, the upper nibble of that byte, and the lower nibble of A, in that order.



;RRD
:{{Opcodelisttop}}
{{Opcode|opdesc=RRD
 |ad1=-
 |ad2=-
 |status=S
 |c=-
 |n=0
 |pv=P
 |h=0
 |z=S
 |s=S
 |tstates=18
}}
|}
:Same as RLD, but the order is: the lower nibble pointed to by HL, the lower nibble of the A, and the upper nibble of the byte.



;CPL (ComPLement)
:{{Opcodelisttop}}
{{Opcode|opdesc=CPL
 |ad1=-
 |ad2=-
 |status=S
 |c=-
 |n=1
 |pv=-
 |h=1
 |z=-
 |s=-
 |tstates=4
}}
|}
:Inverts the contents of the accumulator.



;NEG (NEGate)
:{{Opcodelisttop}}
{{Opcode|opdesc=NEG
 |ad1=-
 |ad2=-
 |status=S
 |c=!
 |n=1
 |pv=!
 |h=S
 |z=S
 |s=S
 |tstates=8
}}
|}
:Subtracts the contents of the accumulator from zero, making it negative for the purpose of two's complement. P/V is set if A previously held $80. C is set if accumulator did not previously hold $00.



;CCF (Craunch Carry Flag)
:{{Opcodelisttop}}
{{Opcode|opdesc=CCF
 |ad1=-
 |ad2=-
 |status=S
 |c=!
 |n=0
 |pv=-
 |h=!
 |z=-
 |s=-
 |tstates=4
}}
|}
:Inverts the carry flag. (Does not, as might be assumed, clear it!) Also sets H to the previous value of the carry flag.



;SCF (Set Carry Flag)
:{{Opcodelisttop}}
{{Opcode|opdesc=CCF
 |ad1=-
 |ad2=-
 |status=S
 |c=1
 |n=0
 |pv=-
 |h=0
 |z=-
 |s=-
 |tstates=4
}}
|}
:Sets the carry flag.



;BIT
:{{Opcodelisttop}}
{{Opcode|opdesc=BIT b,r
 |ad1=Immediate
 |ad2=Register
 |status=S
 |c=-
 |n=0
 |pv=!
 |h=1
 |z=!
 |s=!
 |tstates=8
}}
{{Opcode|opdesc=BIT b,(HL)
 |ad1=Immediate
 |ad2=Indirect
 |status=S
 |c=-
 |n=0
 |pv=!
 |h=1
 |z=!
 |s=!
 |tstates=12
}}
{{Opcode|opdesc=BIT b,(IXY+d)
 |ad1=Immediate
 |ad2=Indexed
 |status=S
 |c=-
 |n=0
 |pv=!
 |h=1
 |z=!
 |s=!
 |tstates=12
}}
|}
:Tests if a bit is set on target value. The first parameter states which bit. The second can be any 8-bit register, or the location in memory pointed to by HL or indexed by IX or IY. Sets Z if specified bit was 0. S and P/V are destroyed.



;SET
:{{Opcodelisttop}}
{{Opcode|opdesc=SET b,r
 |ad1=Immediate
 |ad2=Register
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=8
}}
{{Opcode|opdesc=SET b,(HL)
 |ad1=Immediate
 |ad2=Register
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=!
 |s=!
 |tstates=15
}}
{{Opcode|opdesc=SET b,(IXY+d)
 |ad1=Immediate
 |ad2=Indexed
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=23
}}
{{Opcode|opdesc=SET r,b,(IX+d)
 |ad1=Immediate
 |ad2=Indexed
 |status=U
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=?
}}
|}
:Sets the numbered bit on target value. The possible targets are the same as BIT. The final variant is undocumented and stores the result in a register as well as performing the SET.



;RES (RESet)
:{{Opcodelisttop}}
{{Opcode|opdesc=RES b,r
 |ad1=Immediate
 |ad2=Register
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=8
}}
{{Opcode|opdesc=RES b,(HL)
 |ad1=Immediate
 |ad2=Register
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=!
 |s=!
 |tstates=15
}}
{{Opcode|opdesc=RES b,(IXY+d)
 |ad1=Immediate
 |ad2=Indexed
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=23
}}
{{Opcode|opdesc=RES r,b,(IX+d)
 |ad1=Immediate
 |ad2=Indexed
 |status=U
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=?
}}
|}
:Resets the numbered bit on target value. The possible targets are the same as BIT.



;DAA (Decimal Adjust Accumulator)
:{{Opcodelisttop}}
{{Opcode|opdesc=DAA
 |ad1=-
 |ad2=-
 |status=S
 |c=!
 |n=-
 |pv=P
 |h=!
 |z=S
 |s=S
 |tstates=8
}}
|}
:Modifies the contents of the accumulator based on the flags and the previous operation to correct for binary coded decimal.



;MUL
:{{Opcodelisttop}}
{{Opcode|opdesc=MUL
 |ad1=-
 |ad2=-
 |status=E
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=?
}}
|}
:Next extended opcode. Multiplies HL by DE, leaving the high word of the result in HL and the low word in DE. Does not alter any flags. 



;SWAPNIB
:{{Opcodelisttop}}
{{Opcode|opdesc=SWAPNIB
 |ad1=-
 |ad2=-
 |status=E
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=?
}}
|}
:Next extended opcode. Swaps the high and low nibbles of the accumulator.

=== Control Flow ===
;JP (JumP)
:{{Opcodelisttop}}
{{Opcode|opdesc=JP nn
 |ad1=Address
 |ad2=-
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=10
}}
{{Opcode|opdesc=JP (HL)
 |ad1=Register
 |ad2=-
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=4
}}
{{Opcode|opdesc=JP (IXY)
 |ad1=Register
 |ad2=-
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=8
}}
|}
:Jumps (sets the PC) to the given address. The address can be given immediately or read from HL, IX, or IY. Note that although the variants that use register pairs ''look'' like they are using indirect addressing, JP (HL) jumps to the address stored in the register HL, not the address stored at the address HL points to.



;JP cc 
:{{Opcodelisttop}}
{{Opcode|opdesc=JP Z/NZ/NC/C/PO/PE/P/M, nn
 |ad1=Address
 |ad2=-
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=10
}}
|}
:Conditionally jumps (sets the PC) to the given address. The condition is set in terms of the flags: Zero (Z, NZ), Carry (C, NC), Parity (PO, PE), and Sign (P/M). The address can only be given immediately for a conditional jump.
 


;JR (Jump Relative)
:{{Opcodelisttop}}
{{Opcode|opdesc=JR nn
 |ad1=Immediate
 |ad2=-
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=12
}}
{{Opcode|opdesc=JR C/NC/Z/NZ, nn
 |ad1=Immediate
 |ad2=-
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=12
}}
|}
:Jumps to an alternate address by ''adding'' the parameter to the PC - in other words the parameter is an adjustment, not an absolute address. When used in an assembler with labels the syntax should be the same as JP. The JR address can only be given immediately. Conditions are legal, but only those based on carry and zero.



;DJNZ (Decrement and Jump if Not Zero)
:{{Opcodelisttop}}
{{Opcode|opdesc=DJNZ n
 |ad1=Immediate
 |ad2=-
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=13
}}
|}
:Decrements B then performs JR NZ.. to the given address. Used for encapsulating loops.



;CALL
:{{Opcodelisttop}}
{{Opcode|opdesc=CALL nn
 |ad1=Address
 |ad2=-
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=17
}}
{{Opcode|opdesc=CALL Z/NZ/C/NC/PO/PE/P/M, n
 |ad1=Address
 |ad2=-
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=17
}}
|}
:Like JP (including the ability to have conditions), but PUSHes the PC before jumping. Used for subroutine calls. 
:* If a subroutine ends with a CALL to another subroutine immediately before the RET, it is more efficient to JP to the other subroutine and allow its RET to return from the whole combination. This might make high-level programmers queasy but your compiler already does it (tail call optimization)



;RET
:{{Opcodelisttop}}
{{Opcode|opdesc=RET
 |ad1=-
 |ad2=-
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=10
}}
{{Opcode|opdesc=RET Z/NZ/C/NC/PO/PE/P/M
 |ad1=-
 |ad2=-
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=11
}}
|}
:POPs the PC from the stack, returning from a previous CALL. This can also accept the same conditions as JP.



;RETI
:{{Opcodelisttop}}
{{Opcode|opdesc=RETI
 |ad1=-
 |ad2=-
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=14
}}
|}
:Returns from an interrupt service routine.



;RETN
:{{Opcodelisttop}}
{{Opcode|opdesc=RETN
 |ad1=-
 |ad2=-
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=14
}}
|}
:Returns from a non-maskable interrupt service routine.



;RST (ReSTart)
:{{Opcodelisttop}}
{{Opcode|opdesc=RST n
 |ad1=Immediate
 |ad2=-
 |status=S
 |c=?
 |n=?
 |pv=?
 |h=?
 |z=?
 |s=?
 |tstates=11
}}
|}

:Performs a CALL to a routine located at one of eight fixed locations in the zero page. This is located in ROM, and on the Spectrum only a limited number of values are useful to call built-in ROM routines. 



;NOP (No OPeration)
:{{Opcodelisttop}}
{{Opcode|opdesc=NOP
 |ad1=-
 |ad2=-
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=4
}}
|}
:Does nothing.



;HALT
:{{Opcodelisttop}}
{{Opcode|opdesc=HALT
 |ad1=-
 |ad2=-
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=4
}}
|}
:Suspends the CPU until an interrupt is received.



;DI (Disable Interrupts)
:{{Opcodelisttop}}
{{Opcode|opdesc=DI
 |ad1=-
 |ad2=-
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=4
}}
|}
:Disables maskable interrupts.



;EI (Enable Interrupts)
:{{Opcodelisttop}}
{{Opcode|opdesc=RETN
 |ad1=-
 |ad2=-
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=14
}}
|}
:Enables maskable interrupts.



;IM (Interrupt Mode)
:{{Opcodelisttop}}
{{Opcode|opdesc=IM n
 |ad1=Immediate
 |ad2=-
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=8
}}
|}
:Sets interrupt handling mode. The default for Next is 1. 2 is used for user defined interrupt service routines. IM 0 is useless on Next (and pretty much everything else, to be honest)



=== Input and Output ===
;IN r, (c); OUT (c), r
:{{Opcodelisttop}}
{{Opcode|opdesc=IN r, (c)
 |ad1=Register
 |ad2=Register
 |status=S
 |c=-
 |n=0
 |pv=P
 |h=0
 |z=S
 |s=S
 |tstates=12
}}
{{Opcode|opdesc=OUT (c),r
 |ad1=Register
 |ad2=Register
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=12
}}
|}

:Inputs or outputs a byte value from the 16-bit port number given in BC. R can be any 8-bit register. Note that the port number is given in BC even though the instruction refers only to C. Some assemblers will allow the instruction to be written with "(bc)" instead of "(c)" as a reminder.



;IN (c); OUT (c), 0
:{{Opcodelisttop}}
{{Opcode|opdesc=IN (c)
 |ad1=Register
 |ad2=-
 |status=U
 |c=-
 |n=0
 |pv=P
 |h=0
 |z=S
 |s=S
 |tstates=?
}}
{{Opcode|opdesc=OUT (c),0
 |ad1=Register
 |ad2=Immediate
 |status=U
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=?
}}
|}
:Undocumented opcodes. The IN variation performs an input, but does not store the result, only setting the flags. The OUT variation outputs 0 on the port. This is the only number that can be output to a port in immediate mode.



;IN a, (n); OUT (n), a
:{{Opcodelisttop}}
{{Opcode|opdesc=IN A, (n)
 |ad1=Accumulator
 |ad2=Immediate
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=11
}}
{{Opcode|opdesc=OUT (n),A
 |ad1=Immediate
 |ad2=Accumulator
 |status=S
 |c=-
 |n=-
 |pv=-
 |h=-
 |z=-
 |s=-
 |tstates=11
}}
|}
:Inputs or outputs the byte value in A from a 16-bit port number where the lower byte is N and the upper byte is A. This is only likely to be useful in cases where the upper byte of the port number is not relevant.



;INI (INput and Increment)
:{{Opcodelisttop}}
{{Opcode|opdesc=INI
 |ad1=-
 |ad2=-
 |status=S
 |c=-
 |n=1
 |pv=!
 |h=!
 |z=!
 |s=!
 |tstates=16
}}
|}
:Inputs a value from port BC into memory at the address stored in HL, then increments HL and decrements B. Because B is decremented and is part of the port number, the port number for future INI instructions will change unless it is reset. Z is set if B reached 0; S, H, and P/V are destroyed.



;INIR (INput and Increment Repeated)
:{{Opcodelisttop}}
{{Opcode|opdesc=INIR
 |ad1=-
 |ad2=-
 |status=S
 |c=-
 |n=1
 |pv=!
 |h=!
 |z=1
 |s=!
 |tstates=21x+16
}}
|}
:Loops INIR until B reaches 0. Because B is decremented during this process and is part of the port number, this is unlikely to be useful except when the upper byte of the port number is not relevant.



;IND, INDR (INput and Decrement, INput and Decrement Repeated)
:{{Opcodelisttop}}
{{Opcode|opdesc=IND
 |ad1=-
 |ad2=-
 |status=S
 |c=-
 |n=1
 |pv=!
 |h=!
 |z=!
 |s=!
 |tstates=16
}}
{{Opcode|opdesc=INDR
 |ad1=-
 |ad2=-
 |status=S
 |c=-
 |n=1
 |pv=!
 |h=!
 |z=1
 |s=!
 |tstates=21x+16
}}
|}
:Behave like INI and INIR except that HL is decremented instead of incremented.



;OUTI (Out and Increment), OTIR (Out and Increment Repeated), OUTD (Out and Decrement), OTDR (Out and Decrement Repeated)
:{{Opcodelisttop}}
{{Opcode|opdesc=OUTI
 |ad1=-
 |ad2=-
 |status=S
 |c=-
 |n=1
 |pv=!
 |h=!
 |z=!
 |s=!
 |tstates=16
}}
{{Opcode|opdesc=OTIR
 |ad1=-
 |ad2=-
 |status=S
 |c=-
 |n=1
 |pv=!
 |h=!
 |z=1
 |s=!
 |tstates=21x+16
}}
{{Opcode|opdesc=OUTD
 |ad1=-
 |ad2=-
 |status=S
 |c=-
 |n=1
 |pv=!
 |h=!
 |z=!
 |s=!
 |tstates=16
}}
{{Opcode|opdesc=OTDR
 |ad1=-
 |ad2=-
 |status=S
 |c=-
 |n=1
 |pv=!
 |h=!
 |z=1
 |s=!
 |tstates=21x+16
}}
|}
:Behave like INI, INIR, IND, INDR except that they output instead of input and B is decremented '''before''' the output instead of after.



;OUTINB (Out and Increment with No B)
:{{Opcodelisttop}}
{{Opcode|opdesc=OUTINB
 |ad1=-
 |ad2=-
 |status=E
 |c=?
 |n=?
 |pv=?
 |h=?
 |z=?
 |s=?
 |tstates=?
}}
|}
:Next extended opcode. Behaves like OUTI, but doesn't decrement B.

=== Undocumented extension opcodes ===

These opcodes have been mentioned by developers on the project but not documented. 

;PIXELAD
:{{Opcodelisttop}}
{{Opcode|opdesc=PIXELAD
 |ad1=-
 |ad2=-
 |status=E
 |c=?
 |n=?
 |pv=?
 |h=?
 |z=?
 |s=?
 |tstates=?
}}
|}

;PIXELDN
:{{Opcodelisttop}}
{{Opcode|opdesc=PIXELDN
 |ad1=-
 |ad2=-
 |status=E
 |c=?
 |n=?
 |pv=?
 |h=?
 |z=?
 |s=?
 |tstates=?
}}
|}